<t> o 3 </> O tOWi J. D. Ryder / Charles M. Thomson Prentice Hall Electronic Circuits and Systems Electronic Circuits and Systems J. D. Ryder Formerly Professor of Electrical Engineering Michigan State University East Lansing. Michigan Charles M. Thomson Formerly Senior Dean of Instruction Wentworth Institute and Wentworth College of Technology Boston, Massachusetts PRENTICE-HALL, INC., Englewood Cliffs, New Jersey Library of Congress Cataloging In Publication Data Ryder, John Douglas (date) Electronic circuits and systems. Includes index. 1. Electronics. 2. Semiconductors. 3. Electronic circuits. I. Thomson. Charles M., joint author. II. Title. TK781S.R89 ISBN 0-13-250407-3 1 3 NOV 1987 © 1976 by PRENTICE-HAL Englewood Cliffs, New Jersey All rights reserved. No part o may be reproduced in any for without permission in writing 10 987654321 Printed in the United States of America PRENTICE-HALL INTERNATIONAL, INC., London PRENTICE-HALL OF AUSTRALIA, PTY. LTD., Sydney PRENTICE-HALL OF CANADA, LTD., Toronto PRENTICE-HALL OF INDIA PRIVATE LIMITED, New Delhi PRENTICE-HALL OF JAPAN, INC., Tokyo PRENTICE-HALL OF SOUTHEAST ASIA (PTE.) LTD., Singapore Contents : Preface xiii CHAPTER The Semiconductor Diode 1.1 Eleclrons; Photons I 1.2 Atoms 2 1.3 Crystals 3 1.4 Mclals, Insulators, and Semiconductors 4 1.5 Conduction in Silicon and Germanium 5 1.6 The Forbidden Energy 7 1.7 n and p Semiconductors 8 1.8 Purification of a Semiconductor 10 1.9 Manufacture of a pn Junction 1 1 1.10 The Junction Diode 1 1 1.11 The Diode Voliage-Currenl Equation 13 1.12 Zener Diodes 15 1.13 Light-Emitting Diodes. 16 1.14 Photodiodcs 16 1.15 Capacitance Effects in the pn Diode 17 1. 16 General Comments 17 vi Contents CHAPTER d£ The Diode as Rectifier and Switch 21 2.1 The Ideal Diode Model 21 2.2 The Half-Wave Rectifier Circuit 22 2.3 The Full-Wave Rectifier Circuit 24 2.4 The Bridge Rectifier Circuit 25 2.5 Measurement of the Ripple in the Rectifier Circuit 26 2.6 The Capacitor Filter 27 2.7 The n Filter 31 2.8 The n-R Filter 34 2.9 The Voltage-Doubling Rectifier Circuit 35 2.10 Rectifying AC Voltmeters 37 2.11 Diode Wave Clippers 38 2.12 Diode Clampers 41 2.13 Review 42 CHAPTER O Models for Circuits 48 3.1 The Black Box Concept 48 3.2 Active One-Port Models: the Voltage-Source Circuit 50 3.3 Active One-Port Models: the Current-Source Circuit 51 3.4 Maximum Power Output 53 3.5 The Two-Port Network 54 3.6 The //-Parameter Equivalent Circuit 56 3.7 Power in Decibels 58 3.8 Comments 60 CHAPTER *T Junction Transistors as Amplifiers 64 4.1 Transistor Voltage and Current Designations 64 4.2 The Junction Transistor 65 4.3 The Reverse Saturation Current in Transistors 67 4.4 The Volt-Ampere Curves of a Transistor 67 4.5 The Current Amplification Factors 69 4.6 Relations Between the Amplification Factors 71 4.7 The Load Line and Q Point 72 4.8 The Basic Transistor Amplifiers 74 4.9 Simplification of the Equivalent C-E Circuit 75 Contents vii 4.10 The Transconductancc g m 77 4.11 The Common-Emitter Amplifier 78 4.12 Performance or a C-E Amplifier 80 4.13 Relation Between A, and A,. 81 4.14 Conversion of the /; Parameters 81 4.15 The Common-Base Transistor Amplifier 82 4.16 Performance of the C-B Amplifier 84 4.17 The Common-Collector Amplifier 85 4.18 Performance of the C-C Amplifier 87 4.19 Comparison of Amplifier Performance 88 4.20 Transistor Manufacturing Techniques 89 4.21 Comments 92 CHAPTER DC Bias for the Transistor 96 5.1 Choice of the Quiescent Point 96 5.2 Variation of the Q Point 99 5.3 Fixed Transistor Bias 100 5.4 The Four- Resistor Bias Circuit 102 5.5 Design of a Fixed-Bias Circuit 105 5.6 Design of a Bias-Stabilized C-E Amplifier 107 5.7 Voltage Feedback Bias 1 10 5.8 Design of a Voltage-Feedback Bias Circuit 1 12 5.9 Bias for the Emitter Follower 112 5.10 Design of the Emitter Follower Circuit 1 14 5.11 Comments 115 CHAPTER O The Field-Effect Transistor 6.1 The Junction Field-Effect Transistor 120 6.2 The MOS Field-Effect Transistor 123 6.3 Symbols for the FET 125 6.4 The Load Line for the FET 125 6.5 Obtaining Bias for the FET 127 6.6 The Four-Resistor Bias Network 129 6.7 Design Examples 130 6.8 The FET as an Amplifier 132 6.9 Circuit Characteristics of the FET 132 120 viii CHAPTER Contents 6.10 The Equivalent Circuit or the FET 135 6.11 The Common-Source Amplifier 136 6.12 The Common-Drain Circuit 137 6.13 Design Example 140 6.14 Using the FET as a Variable Resistance 142 6.15 Summary 142 CHAPTER The Vacuum Tube 145 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 145 Circuit Notation for the Vacuum Tube The Triodc 146 Triode Characteristics 148 The Pentode 150 The Equivalent Circuit 152 The Triode Common-Cathode Amplifier 153 The Pentode Common-Cathode Amplifier 154 The Cathode Follower 155 The Grounded Grid Amplifier 157 The Cathode-Ray Tube 159 Comments 161 Contents CHAPTER ix O Frequency Response of RC Amplifiers 164 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13 8.14 Cascaded Amplifiers 164 The Amplifier Passband 165 The Frequency Plot 167 Low-Frequency Response 168 The Low-Frequency Limit 172 Low-Frequency Response for the FET and Vacuum-Tube Amplifiers 175 The Unbypassed Emitter Resistor 177 High-Frequency Equivalent Circuits; the Miller Effect 180 High- Frequency Response 182 The Frequency Limit of the Transistor 185 The Common-Base Connection at High Frequencies 188 Bandwidth of Cascaded Amplifiers 189 Frequency Emphasis and De-Emphasis 191 Review 194 ' Negative Feedback in Amplifiers 199 9.1 The Black Box with Feedback 199 9.2 Stabilization of Gain by Negative Feedback 202 9.3 Bandwidth Improvement with Negative Feedback 204 9.4 Reduction of Nonlinear Distortion 206 9.5 Control of Amplifier Output and Input Resistances 207 9.6 A Current Series-Feedback Circuit 209 9.7 Voltage Shunt-Feedback Circuit 212 9.8 Voltage Feedback with the FET 213 9.9 The Emitter Follower as a Feedback Amplifier 215 9.10 Multiple-Stage Feedback 216 9.11 Amplifier Gain Stability with Feedback 217 9.12 Gain and Phase Margin 220 9.13 Comments 221 CHAPTER 10 Integrated Amplifiers • 225 10.1 The Integrated Amplifier 225 10.2 The Differential Amplifier 228 10.3 Rejection of Common-Mode Signals 232 10.4 A Constant-Current Circuit for R R 236 10.5 Voltage References 237 10.6 The DC Level Shifter 237 10.7 The Operational Amplifier 238 10.8 The Unity-Gain Isolator 242 10.9 The Summing Operation 242 10.10 The Integration Operation 243 10.11 The Comparator 245 10.12 A Millivoltmctcr 245 10.13 Frequency Compensation 246 10.14 The Slew Rate 247 10.15 Offset Voltage and Current 249 10.16 Definition of Terms 249 10.17 The Darlington Compound Transistor 250 10.18 The Cascode Amplifier 252 10.19 Silicon Integrated Circuits 253 10.20 Passive Elements 255 10.21 Comments 256 Contents CHAPTER A. A. Tuned and Video Amplifiers 11. 1 Band-Pass Amplifiers 261 11.2 The Parallel-Resonant Circuit 263 11.3 Bandwidth of the Resonant Circuit 265 11.4 The Single-Tuned Transistor Amplifier 268 11.5 The Double-Tuned Transformer 269 11.6 The Pulse Waveform 271 11.7 The Shunt-Peaked Video Amplifier 273 11.8 The Series-Peaked Video Amplifier 277 11.9 Review 278 261 CHAPTER J. ^ Power Amplifiers 12.1 Defined Operating Conditions 283 12.2 The Ideal Transformer 285 12.3 Power Relations in the Class A Amplifier 286 12.4 Voltage Limitations 290 12.5 Effect of the Thermal Environment 290 12.6 Determination of Output Distortion 293 12.7 The Push-Pull Circuit and Class B Operation 297 12.8 Performance of a Class B Push-Pull Amplifier 300 12.9 Output Circuits Without Transformers 302 12.10 Phase Inverters for Push-Pull Input 304 12.11 Complementary Symmetry Circuits 305 12.12 The Class B Linear Radio-Frequency Amplifier 307 12.13 Summary 308 283 CHAPTER J. yj Oscillator Principles 13.1 Oscillator Feedback Principles 313 13.2 The Hartley and Colpitts Oscillators 316 13.3 Practical Transistor Oscillators 316 13.4 Crystal Control of Frequency 319 13.5 Resistance-Capacitance Feedback Oscillator 322 13.6 Comments 323 313 Contents xi CHAPTER 14 Modulation and Detection 326 14.1 Fundamentals of Modulation 326 14.2 The Frequency Spectrum in AM 327 14.3 The Power Spectrum in AM 330 14.4 The Diode Modulator for AM 331 14.5 High Power-Level AM Modulation 333 14.6 Linear Detection for AM Signals 334 14.7 Automatic Volume Control (AVC) 336 14.8 The Single-Sideband System of Modulation 337 14.9 Frequency Translation; the Product Detector 339 14.10 The Frequency Spectrum of FM Signals 341 14.11 Bandwidth of FM Signals 342 14.12 Generation of FM Signals 344 14.13 The Limitcr and Discriminator for FM Detection 344 14.14 The Ratio Detector for FM 347 14.15 Automatic Frequency Control (AFC) 348 14.16 Comments 349 CHAPTER 15 Radio Systems 3S3 15.1 Noise 353 15.2 Information in Signals 354 15.3 Information Capacity of a Channel 355 15.4 An AM Transmitter 357 15.5 The Superheterodyne Receiver 358 15.6 The SSB Transmitter 362 15.7 An SSB Transceiver 363 15.8 AM Versus FM 366 15.9 FM Systems 367 15.10 A Radar System 368 15.11 Frequency Classification for Radio Signals 371 CHAPTER 16 Digital Circuits 374 16.1 Binary Numbers 374 16.2 Binary Arithmetic 377 16.3 Binary Codes 378 16.4 Other Number Systems 379 xii CHAPTER 16.5 16.6 16.7 16.8 16.9 16.10 16.11 16.12 16.13 16.14 16.15 16.16 16.17 16.18 16.19 16.20 16.21 16.22 16.23 16.24 16.25 16.26 16.27 16.28 16.29 16.30 16.31 17 17.1 17.2 17.3 17.4 17.5 17.6 17.7 Contents Scries and Parallel Processing of Bits 381 Logic Operations in Addition 382 Logic Switches 383 Logic Voltage Levels 386 Diode Logic (DL) Gages 386 The not or Inversion Operation 388 Integrated Logic Circuits 389 Diode-Transistor Logic (DTL) 390 Resistance-Transistor Logic (RTL) 392 Transistor-Transistor Logic (TTL) 393 Emitter-Coupled Logic (ECL) Circuits 394 CMOS Logic Circuits 395 nand and nor Circuits with CMOS Logic 396 CMOS Manufacture 398 The Adder Circuit as a Logic System 399 Multivibrators 400 The Bistable Multivibrator or Flip-Flop 401 The RS Flip-Flop 402 The T or Toggling Flip-Flop 403 The JK Flip-Flop 405 The One-Shot or Monostablc Multivibrator 407 The Astable Multivibrator 408 Synchronization of the Free-Running Multivibrator 410 The Schmitt Trigger Circuit 41 1 The Shift Register 412 Decoding Matrices 413 Decimal Counting 414 Power Control The Silicon-Control Rectifier (SCR) 422 SCR Characteristics 423 The Unijunction Transistor (UJT) 425 Triggering the SCR 427 The Controlled Polyphase Rectifier 430 Shunt- Wound DC Motor Control 431 Comments 432 Index 422 Preface 435 This book has been written to provide the electronic technician with a broad and basic understanding of the diode and transistor and other devices, the circuits, and the systems in which they are employed in the electronics field. The technician is often most interested in practical electronic applica- tions in the real world. To foster this interest we have included selected appli- cations with the solid-state and transistor theory. The concept of electrical equivalent circuits or black boxes is developed early in the text and consistently applied. To demonstrate the similarity of the active electronic devices, only one circuit model is used to describe all three amplifying devices, the bipolar transistor, the field-effect transistor, and the vacuum lube. The circuit model employed is the g m -controlled constant-cur- rent source. It is simplified in form for easy understanding of the circuit opera- tion, but is sufficiently accurate for basic circuit design procedures. The material presented, and the terminology employed, is intended to acquaint the student with practical usage in the field. The mathematics involved is restricted to algebra and simple trigonometry. Derivations arc rather thoroughly developed. In this manner the student can discover how algebra is employed in reasoning and leads to results which have electrical meaning. Many worked examples provide the student with a knowledge of the circuit conditions encountered under a variety of operating conditions. It is expected that the student will have completed or is currently taking a course in ac circuit fundamentals. xiii xiv Preface Fundamental material on the solid-state conduction process is introduced in Chapter I . This provides curious students with answers to the why and how of diodes and transistors. Diodes result from the ability to transform silicon and germanium into n and p forms, and diode theory and application are introduced in Chapter 2. Rectifier circuits arc presented, along with the function of filter circuits. This material is introduced here since it demonstrates an important application of the diode, as well as furnishing source material for early laboratory experi- ments. The idea of a black box as an equivalent model of an electrical circuit or device is introduced in Chapter 3. One-port and two-port forms are discussed, and the equivalent circuit /(-parameters are brought forward. In Chapter 4, the operation of the transistor is developed, and the equiva- lence between the transistor and the /j-parameter two-port circuit is then shown. Thereafter the common-emitter h parameters and the g m model are used for amplifier analysis throughout the book. The low-frequency perfor- mance of the three basic amplifier forms is developed and compared. Tech- niques used in the manufacturing of several modern forms of the transistor arc discussed. The necessity for choice of an operating point in the mid-region of the transistor output curves to obtain linear and undislorted response is shown in Chapter 5. Bias circuits which establish and maintain this operating point are found. Several circuits are treated as design examples. The important field-effect transistor is covered in Chapter 6. The g m cur- rent-source model is used again. Bias circuits and complete amplifier designs are developed. Building on the previous circuit theory, and again employing the g m model, the vacuum tube is introduced in Chapter 7. Triode and pentode circuits are briefly discussed. The cathode-ray lube is also introduced here. The response of amplifiers over broad frequency ranges is considered in Chapter 8 and the problems which arise in multistage amplifiers are also introduced. The efTect of the internal parasitic capacitances, always present in all devices, on the response of the amplifying devices at high frequencies is discussed. Feedback is of the utmost importance in most electronic applications, and sufficient background has been developed to permit a discussion of feedback in Chapter 9. The performance improvements obtained with negative feed- back are shown, and we also introduce some of the problems of amplifier instability. Feedback operation in multistage amplifiers is given special atten- tion. The universally used integrated or monolithic differential amplifiers are presented in Chapter 10. A discussion of the basic circuits within the usual Preface amplifier, and the methods of manufacture, follows. The operational ampli- fier, and a few of its many applications are included. Chapter 1 1 provides coverage of the frequency response of transistors in tuned radio-frequency amplifiers. Also included are the rectangular pulse wave form and its use in video amplifiers or in data circuits. Power amplifiers and their associated heat-removal problems are consid- ered in Chapter 12. General push-pull circuits as well as modern transfor- merless circuits are covered. The class B linear radio-frequency amplifier is also discussed because of its popularity in increasing power at radio frequen- cies. Feedback is used to create the several forms of tuned oscillator circuits, crystal oscillators, and the laboratory form of RC oscillator presented in Chapter 13. Having established a foundation of various building-block electronic cir- cuits, we proceed to a study of modulation and detection of amplitude-modu- lated and frequency-modulated signals in Chapter 14. Frequency spectra and bandwidth requirements for the various signals are shown, as well as methods of generation of the modulated signals. Fn Chapter 15 the concepts of information content of a signal and the information capacity of a channel are introduced. The previously-developed basic circuits are combined in several complete radio systems, as examples. Chapter 16 departs from the realm of the continuous or analog signal and introduces the binary code, the binary pulse signal and logic circuits for data manipulation and computation. Modern ECL, TTL, and CMOS forms of logic circuits are included. Logic circuit applications in adding, flip-flop and counting circuits are used as examples. The text concludes with Chapter 17 which details the characteristics of power-switching devices and their applications in several areas of power control. Questions to encourage student review and extensive lists of problems are supplied at the end of each chapter. John D. Ryder Charles M. Thomson Electronic Circuits and Systems 1 The Semiconductor Diode In recent years we have learned a great deal about electrical conduction in solids and have been able to make semiconductor materials having electrical properties that normally do not occur in nature. From this research into the electrical properties of solids, the pn junction diode has been developed. It is widely applied as a rectifier and as a device with a nonlinear voltage- current characteristic. Principles found in the development of the diode are also employed in the transistor. 1.1 Electrons; Photons Electronic science had its beginning in 1883 when Edison observed that a current would pass between a metal plate and the heated filament in one of his lamps if the plate was made positive in relation to the filament. This "Edison effect" was due to the flow of negative particles, later named elec- trons. The electron is now accepted as the fundamental unit of electric charge, negative in nature and designated as —e. It is so small that 6.25 x 10 2s electrons must pass per second to represent a current of one ampere. The physical form of an electron is unknown but we shall assume that it is a spherical particle with a mass measured as 9.11 X 10" 3 ' kilogram. The photon is a bundle of radiant energy appearing as light, heat, X rays, and other electromagnetic radiation. The size of the energy package is in- versely related to the wavelength of the radiation and is measured in joules. The Semiconductor Diode 1.2 Atoms The chemical elements are built of atoms. The Bohr theory of atom.c struc- ture proposes a central nucleus of positive electrical charge and mass, around which electrons move in definite orbits. The positive charge of the nucleus is due to protons, each having a positive charge equal to that of the electron. The proton has a mass approximately equal to that of the hydrogen atom. Additional mass is added to the nucleus of heavier elements by the presence or uncharged particles known as neutrons. Each element has a number of protons in its nucleus corresponding to its atomic number, which can be found in the periodic table. A normal atom is electrically neutral since the number of protons in the nucleus .s equal to the number of electrons in the surrounding orbits. There is a fixed amount or level of rotative energy associated with each orbif electrons in the innermost orbits close to the nucleus have the least energy and those at greater distance from the nucleus have greater energy. Orbits with common energy levels are called shells or rings. Each shell or ring has positions for a definite number of electrons. When these posit.ons are occupied by electrons, the shell is said to be filled. The inner shells are normally filled and their electrons are shielded from external forces by the charges of the outer shell electrons. The electrons in the outermost shell are called the wlenee electrons since it is these outer electrons that contact the neighboring atoms and give the element its expected properties in forming chemical compounds. Hydrogen has only one proton and one electron, and possession of a single electron gives hydrogen a valence of one and places it in Group I of the periodic table. Copper, another Group I element with one valence elec- tron in its outer shell, has its 29 electrons grouped as Shell K L No. of electrons 2 8 M 18 N 1 The elements found in Group I have many unfilled positions in the outer shell and easily join with other elements having greater numbers of valence electrons. Thus Group I elements are considered chemically active Elements of Group VIII such as helium, neon, and argon have filled outer shells with eight electrons. There are no unfilled energy levels available to valence electrons of other atoms and Group VIII elements are chemically inactive. . ... The Group IV elements include our important semiconductors, silicon and germanium, with the following electron arrangement in the shells: Crystals K L M N Carbon 2 4 Silicon 2 8 4 Germanium 2 8 18 4 The four electrons in the valence shell provide desirable semiconductor properties. Even carbon becomes a semiconductor when in diamond form and heated sufficiently. An atom bombarded by a high velocity electron or other particle carrying sufficient energy may have an electron knocked out of the valence shell. This leaves the atom with a net positive charge of Ye, and the positively charged atom is known as a positive ion. The energy supplied by the bombard- ing particle is known as the ionizing energy. 1.3 Crystals In a liquid there is a random location of the atoms but as an element freezes from the liquid state, the distance between atoms decreases and the binding forces increase. This gives the material its strength as a solid, in many solids the atoms assume regular, lattice-like arrangements much as spheres pack in a box in layered order. The resultant structural arrangement of atoms is called a crystal. Crystals repeat the unit structure, shown in Fig. l.l, as well as other forms. The form for a given clement is determined by the nature of the forces that bind the atoms in the solid. / i— A" y &>C n y— +-> / i *- (a) trfr— X* /. ! *H / k ! ■0sr (b) *L w (c) Figure /./ Unit crystal cells: (a) simple cubic lattice: (b) facc-ccnlercd cubic lattice; (c) body-centered cubic lattice. Mechanical working of a material, such as the stretching of a wire, tends to create a structure of many small crystals. The random boundaries of these individual crystals cause erratic electrical conduction properties. Semi- conductor materials are carefully grown in single crystal form, however, and this ensures that crystal boundaries do not disturb the desired conduction properties. The Semiconductor Diode 1.4 Metals, Insulators, and Semiconductors Our good electrical conductors are metals, such as silver, copper, or gold. In metals the interatomic spacing is so close that the orbits of the outer- most electrons of neighboring atoms overlap and a valence electron will be in the attractive fields of several nuclei. The fields essentially cancel, leaving these outer electrons very loosely held. They are freed from their nuclei by the random thermal vibrations of the atoms at room temperature. Copper and silver have one valence electron and thus we have one electron per atom available to move as a free charge. These metals have about 10 23 atoms per cm 3 and so we have 10 23 electrons per cm 3 as free charges available to move in the conduction process.'" When we apply a voltage to a wire, individual charges move in a random manner toward the positive terminal at low velocity. With the large number of free charges we find that the electrical resistivity of metals is low (see Table 1.1). TABLE 1.1 Electrical Properties of Materials Material Properly Resistivity (fl-m) Silver Conductor 1.6 x 10-8 Germanium Semiconductor 0.6 Silicon Semiconductor 1500 Polystyrene Insulator 10'» There are other materials that bind their valence electrons so tightly that there are few charges able to move at the usual ambient temperatures. With few free charges these materials cannot carry an appreciable current and they are classed as insulators (quartz, porcelain, and polystyrene are examples). 'We shall use the scientific method or notation, stating quantities as small numbers limes powers of 10, to avoid writing many zeros to the right or left of the decimal point. We shall also designate major magnitudes by the following prefixes, used with the unit name, as in w;//metcr ■ 0.01 meter: Multiple Prefix Symbol Multiple Prefix Symbol 10'* tcra T 10-2 ccnti c 10' giga G 10- 3 milli m 10« mega M io-« micro p. (lowercase Greek mu) 10' kilo k io-» nano n 10- > 2 pico P Conduction in Silicon and Germanium 5 In pure form the semiconductors have conduction properties intermediate between the good conductors and the insulators. A pure semiconductor is an insulator at temperatures near absolute zero (— 460°F or — 273°C) but the resistance falls as the temperature rises. Such materials, whose resis- tance decreases with rising temperature, are said to have negative tempera- ture coefficients of resistance. Semiconductors of major importance are silicon and germanium; their properties are compared to a good conductor and to an insulator in Table 1 . 1 . A number of metallic sulfides and oxides and compounds such as gallium arsenide and gallium phosphide are also useful in semiconductor applications. 1.5 Conduction in Silicon and Germanium Our most important semiconductors, silicon and germanium, are from Group IV and they have four valence electrons. They form crystals having covalent bonds between atoms in which the valence electrons are shared in pairs with four adjacent atoms. This is diagrammed in Fig. 1.2. The electrons in the covalent bonds arc spinning on their axes but in opposite directions. The spin creates a magnetic field and the interlocking of these magnetic fields Electron , Covalent , [ / Bond Nucleus ■::::~M y ::: \ i i i ; i i i i i \ i \ i \ i n Figure 1.2 Schematic drawing of covalent bonds in germanium at absolute zero temperature. The Semiconductor Diode 6 provides the binding force of the covalcnt bond that holds the crystal t0g Absolute zero temperature (-460°F or -273°C) all the valence elec- trons of the semiconductor are tightly held in the covalcnt bonds w.th neigh- boring atoms. There are no charges free to move if a voltage is applied. Electrical conduction is not possible and the materials behave as msulators. As the temperature rises to the ambient range (SOT or 27°C), thermal energy is absorbed by the atoms and the electrons of the solid; this energy appears as random vibration or agitation of these particles about thc.r lattice loca- tions Some electrons acquire sufficient energy to break the covalent bond and the electrons become free and mobile. Energy for breakage of a covalent bond may also be supplied by a high voltage across the matenal or by rad.a- tion with photons of appropriate wavelength. When a bond is broken and an electron freed, an electron vacancy is left in the covalent bond. The vacant electron site is called a hole, indicated in Fig 1 3 The hole represents the absence of a negative charge and is attrac- tive to electrons; therefore the hole appears to have a positive charge of -\-e value. i * ♦ l I Nucleus I i Conduction ♦ f * Klcctron f f* CoVJ *c P :» Covalent Bond ' i K k . Hole * • 1 ' Figure 1.3 Formation of a hole. An atom that has lost an electron is a positive ion fixed in the crystal lattice The total material remains electrically neutral, however, s.ncc the number of positive ions is still equal to the number of free electrons. The hole is also considered to be mobile. Examine Fig. 1.4, where a broken covalent bond has left a hole at A. Another electron may move from a bond at B to the hole at A, under the force of a small voltage applied across the material as shown. When the electron fills the hole at A there : is now a hole at B; then another electron may move from a bond at C to the hole at B and the hole has moved to C. In a similar manner an electron may move from a bond at D to the hole at C and so the hole has moved from A to D in stepwise fashion. The Forbidden Energy $$ <*><*> Original Hole / \ Jump2 ^L \ ^«b1«25 --€>- <•><$> V <•> •<\<°" '/>• \ D, JUmp3 <•)<•) <•)<*) Final Hole Location Figure 1.4 Conduction by a hole. The hole and the electron arc both mobile charges that can take part in electrical conduction in these materials. The positive hole progresses toward the negative terminal of an applied voltage, however, while the electron moves toward the positive terminal. In this text we define conventional electric current as a flow of positive charges so that the movement of holes corresponds to a conventional current. Since holes and free electrons are simultaneously produced when a covalent bond is broken, we speak of the process as the generation of elec- tron-hole pairs. This is a natural and inherent process in semiconductors and conduction with charges produced by pair generation is called intrinsic conduction. The number of pairs produced and the intrinsic conductivity are both low at room temperature since intrinsic conduction by holes and electrons is dependent on the thermal agitation of the atoms to provide the energy to break the valence bonds. The process is so sensitive to the temperature that intrinsic current levels may be expected to double for every increase of IO°C or 18°F, limiting the use of silicon devices to 390°F or 200°C, and germa- nium devices to 200°F or 90°C. Intrinsic conduction is not desired in transistor operation and the effect is suppressed by operation of those devices below these maximum tem- perature limits. 1.6 The Forbidden Energy To become free and mobile, a valence electron in a semiconductor must acquire sufficient vibrational energy to break the covalent bond. The break- The Semiconductor Diode n and p Semiconductors age energy of a bond in a given material is a fixed quantity, called E .' 2 ' We cannot have a partially broken bond and so energies less than E are unac- ceptable or forbidden to the valence electrons. As a result, E c is called the forbidden energy or sometimes the gap energy in semiconductors. Measured in electron volts, the forbidden energies of the major semi- conductors are Silicon Germanium l.lSeV 0.75 cV Since the forbidden energy of silicon is greater than that of germanium, more energy is needed to break a covalent bond in silicon and there will be fewer intrinsic charges. Thus silicon has lower intrinsic conductivity at ambient temperatures. 1.7 n and p Semiconductors Germanium is obtained as a by-product in zinc refining and silicon is derived from the manufacture of silicones. Both materials arc highly purified to remove the random impurities of manufacture. To obtain the desired conduction properties, the pure silicon or german- ium is "doped" with minute amounts of selected elements as controlled impurities. Desirable doping elements include boron, aluminum, gallium, and indium; these have three valence electrons and are said to be trivalent impurities. Other doping elements are chosen from arsenic, antimony, and phosphorus; these have five valence electrons and are referred to as penta- valent impurities. The impurities are added at rates of one atom of doping element to 10 ! to 10 8 atoms of semiconductor. The small density of doping atoms causes them to be separated by thousands of semiconductor atoms in every direc- tion and the form of the crystal is not altered by the presence of the impurity atoms. An impurity atom can only find a place in the crystal by substituting for one of the germanium or silicon atoms; it cannot alter the crystal form. When a pcntavalent atom, such as arsenic, substitutes for a silicon atom, there are places in the covalent bonds for only four of its five valence elec- trons and one electron is left over. This is indicated in Fig. 1.5(a). The bind- ing force of this electron to its nucleus is slight and the thermal agitation at room temperature is sufficient to break this electron free. iWc measure Eo and other energies associated with atomic particles in electron rolls (cV). An electron receives I cV of energy when accelerated through 1 V; it receives 500 cV of energy when accelerated through a potential of 5C0 V. This numerical equivalence of potential and energy gained makes the electron volt a convenient measure of energy. The electron volt represents an energy of 1.60 x 10" >» joule. Excess Electron » ; / \ Hole • * \ i \ I Figure I.S Semiconductor with (a) a pcntavalent arsenic impurity; (b) a trivalent indium impurity. By addition of a pentavalent impurity we have created a material having only electrons as free and mobile charges; such a semiconductor is said to be n material. The pentavalent atoms have donated an electron for conduc- tion and are called donor atoms. Since an electron has been removed from the 10 The Semiconductor Diode donor atoms, they remain as positive ions fixed in their crystal positions. When a trivalcnt atom substitutes for a semiconductor atom in a crystal, its three valence electrons enter the covalent bonds with electrons from three neighboring silicon or germanium atoms but an electron vacancy or hole is left in the bond to a fourth neighbor atom, as illustrated in Fig. 1.5(b). At room temperature the built-in hole can be filled by an electron from a nearby bond and this process creates a mobile hole in the adjacent area. The use of a trivalent impurity element has created a material with free holes so that conduction will occur by hole transfer and the impurity semi- conductor is said to be p material. The trivalent impurity atoms accept electrons to fill their bond vacancies and are called acceptor atoms. Since these atoms have acquired an extra electron, they remain fixed in the crystal as negative ions. In an n semiconductor the conduction will be predominantly by electrons and the electrons will be called the majority carriers. There will be a few holes present in an n material due to electron-hole generation at usual ambient temperatures. The holes present in an n material are known as the minority carriers. The conduction in a p material will be primarily due to holes and they are known as the majority carriers. There will be a few electrons present in a p material due to thermal-pair generation: these electrons in a p material are known as the minority carriers. 1.8 Purification of a Semiconductor The purification of germanium or silicon to semiconductor standards is usually done by zone refining in an inert gas atmosphere. If the temperature of a short section of impure rod is raised to the molten state and the molten zone moved slowly, the impurities tend to remain in the molten zone and travel with it to the end of the rod. By multiple repetition of the process, the impurities can be concentrated at one end of the rod. This section is then removed and discarded. To grow single crystal n or p material, the purified semiconductor is melted in a crucible and the desired trivalent or pentavalent impurity added. A small seed crystal is dipped into the molten semiconductor and as it is slowly rotated and withdrawn, a large crystal grows on the seed with the same lattice orientation. This is illustrated in Fig. 1.6(a). The large crystals may be 2 or 3 cm in diameter. Properly oriented, they are sliced by diamond saws into thin wafers. The surfaces are then etched and polished to remove crystal dislocations caused by the sawing process. The Junction Diode 11 p Pellet Junction n Germanium i£ Molten Semiconductor (a) (b) (c) Figure 1.6 (a) Growing the single crystal ; (b) a grown pn junction ; (c) an alloyed junction. 1.9 Manufacture of a pn Junction The semiconductor diode employs the properties of a junction between p and n layers of semiconductor material. In the grown junction process, a crystal is grown from an n melt and at a proper lime ap impurity is added. The p material overrides the n doping and yields a p material. The junction occurs where the n material changes to p, as indicated in Fig. 1.6(b). Alloyed junctions arc produced by fusing a pellet of a p impurity, such as indium, onto the w-silicon or H-germanium wafer. The indium alloys with the semiconductor and creates a thin /^-silicon or /7-germanium layer. The remainder of the pellet serves as a contact to the p side of the junction, as shown in Fig. 1.6(c). In the diffusion process, a semiconductor wafer of /(-impurity type is heated in a furnace with a gaseous atmosphere containing the desired p impurity. At elevated temperature the impurity atoms migrate into the semiconductor and create a p layer in the n wafer. Numbers of large wafers can be processed in one operation, resulting in uniformity of characteristics. There is no crystalline discontinuity at the junction formed between n and p layers in a single crystal. Such a junction cannot be created mechan- ically by forcing two individual crystals together since the junction must be atomic in nature. 7. 10 The Junction Diode Our ability to make n and p materials by controlled impurity additions to a pure semiconductor results in the pn junction, which has the property of one-way conduction. Consider the junction diode of Fig. 1.7 with positive voltage connected to the p region and the negative battery terminal to the 12 The Semiconductor Diode The Diode Voltage-Current Equation 13 Depletion region » ' T 1 n i u -r-| 1 p " / If ++++ _l. + +++ _ ; ++++ , if •t + + + + J ! | ++++ ( i i i i i '» J \ J ! I.Ik ilil 1 rM« + V '■' + V (a) (b) Figure 1.7 (a) Forward voltage across a pn junction; (b) junction with a reverse voltage applied. n region. This is the forward current condition, with the forward current into p shown as l t . There are supplies of electrons in the n region supported by electron flow or injection into n from the negative battery terminal. There are holes in the p region supported by hole injection from the positive terminal. With the voltaee connected, holes move across the junction from p and into the electron-rich n region, where they meet and combine with electrons. But this positive charge has disturbed the neulrality of the n region and so electrons flow from the negative terminal toward the junction to restore the charge balance. This is indicated by the several flows of Fig. 1.8. Likewise, free electrons move from the electron-rich n region across the junction into the p region. This flow has made the p region more negative. We have a current composed of holes in the p region and a negative cur- rent due to electrons in the n region. The holes and electrons are continu- ously replenished from the battery and the movement of these charges to the terminals constitutes the forward current I, into the p and out of the n Figure 1 .8 shows how the number of charges varies with distance from the junction. The currents far from the junction are carried by the majority carriers of each region. Of course, in the metallic wires between diode and battery the current is due to motion of electrons. Electrons are supplied to the n region from the negative battery terminal and electrons are extracted from the covalent bonds at the ^-region terminal by the positive battery potential, in effect injecting holes into the p region. With reverse polarity, the diode has a positive voltage connected to the n region and negative voltage to the p region, as shown in Fig. 1.7(b). With the n region positive, free electrons are attracted away from the n junction. With the p region negative, the free holes are also pulled away from the junction and into the p region. As a result, there is a region extending between x, and .v 2 on both sides of the junction that has been depleted of mobile charges. Accordingly this is called the depletion region. It may be only a small fraction of a millimeter thick but without mobile charges it cannot conduct. Thus with reverse voltage across the diode we have an effective insulating layer at the junction. The depletion region is still subject to electron-hole pair generation, however, due to thermal energy. All such intrinsic charges arc swept out of the region by the applied voltage and this flow is known as the reverse satura- tion current I,. This reverse current depends on the number of broken cova- lent bonds at the operating temperature. The current is small in magnitude but it is strongly dependent on temperature. The pn diode easily passes current in the forward direction and has only a small current in the reverse direction. This is the property of a rectifier diode. Current Distance Along the Bar Figure 1.8 Electron and hole currents in a forward-biased junction. 1.11 The Diode Voltage-Current Equation The current through a pn junction can be predicted by the equation /-JfcMT-l) (1.1) at 80°F or 27°C. The voltage V is positive for forward current and negative for reverse current. With forward voltages greater than 0.1 V we can use a simpler form of 14 The Semiconductor Diode equation as Forward Current I -UP" 0-2) and with reverse voltage more negative than —0.1 V we can use the relation Reverse Current I=-l, (1-3) This identifies the reverse current as the reverse saturation current of the junction. It is dependent on the rate of electron-hole pair generation in the depletion region and is not dependent on the reverse voltage up to the Zener (see Sec. 1.12) breakdown point, which occurs at about -40 V for the typical diode shown in Fig. 1 .9. The current /„ being dependent on the rate of pair generation, is variable with temperature. 10 \ o — — A /, m A , i / 40 -. .f- 20 l 10 ^L 1 * n o < in v 1 t -4jiA -8M 1 "tr fa) (b) Fifiure 1.9 (a) Typical semiconductor diode voll-ampcrc curve (note scale changes); (b) diode circuit symbol. Table 1.2 is calculated by use of Eq. 1.1 and presents the data in terms of the current ratio /,//,. It shows that the diode is a one-way electrical device. The volt-ampere curve of Fig. 1.9 is from actual measurement of a sample diode and the voltage includes resistance drops in the semiconductor material outside the junction region. This accounts for greater voltages than are given in Table 1.2. The diode circuit symbol is shown in Fig. 1.9(b). Zener Diodes 15 TABLE 1.2 Diode Forward Current + V Ifll, I V IfU, 0.04 3.76 0.06 9.38 0.08 21.6 0.10 49.0 0.12 108 0.14 235 0.16 513 0.18 1119 0.20 2440 0.22 5.32 x 10' 0.24 11.6 x 103 0.26 25.3 x 10' 0.28 55.3 x 10' 0.30 120 x 10' 0.35 8.47 x 10' 0.40 5.96 x 10« 0.45 4.19 X 10? 0.50 2.94 x 10» 1.12 Zener Diodes In theory, the reverse current of the pn diode is a constant, /„ and independent of reverse voltage. Actually the diode has a breakdown at some value of reverse voltage. This occurs at —40 V for the diode of Fig. 1.9. The break- down voltage is stable for a given diode. This breakdown is not harmful if the power dissipation in the diode is limited to the rated value and a safe temperature is maintained. The Zener diode circuit symbol is shown in Fig. 1.10(a). The diode voltage cannot exceed the breakdown value and V. at the output terminals will not rise above that level in the circuit of Fig. 1.10(b), regardless of in- creases in V,. The diode current increases and the excess of voltage V, over V, appears as an increased voltage drop in R. Therefore the Zener diode is useful to maintain a fixed voltage across its terminals as a voltage regulator. Its effect is much as if a battery V. was connected across the output terminals whenever V, > V„ as indicated in Fig. 1.10(c). + If It 6 (a) /■ ' (b) K R O WvV- + •& V ' (O Figure 1.10 (a) Zener diode symbol; (b) regulating circuit; (c) illustrating Zener circuit action. 16 The Semiconductor Diode The reverse-voltage region of operation was investigated by Zener and the diode bears his name. The reverse voltage appears across the depletion region and at some value is sufficient to accelerate the thermally generated electrons in the region to a velocity at which they are able to free more elec- tron-hole pairs by collision with covalent bonds. After each collision there is an additional pair of charges and in turn these arc accelerated and collide with atoms, creating still more charges; the current builds up like an ava- lanche. The breakdown voltage can be lowered by increasing the impurity dop- ing. Diodes are available with Zener voltages ranging from about 3 to 200 V and with power ratings from £ to 200 W. 1. 13 Light-Emitting Diodes The gap energy E is acquired by the electron when it is broken free from a covalent bond in a semiconductor (see Section 1 .6). Consequently, when a free electron falls back into a hole in a covalent bond, the electron must give up the same amount of energy. This energy is radiated from the elec- tron as a single photon of light, with the color of the light related to the gap energy of the material. For a gallium arsenide pn diode with E a — l.5eV, the emitted light is a dark red. Green is obtained from a gallium phosphide diode. Because the energies of the electrons vary slightly, the light emitted is not of one wave- length but spreads over a narrow wavelength band. The intensity of the light can be varied with the applied voltage, changing the number of recombina- tions per second. The light is entirely electronic in nature and very fast on-ofF switching is possible. These light-emitting diodes (LEDs) are being used as point sources for numerical readouts for calculators and in alphabetic display devices. 1.14 Photodiodes Reverse-voltage diodes in which the p layer is made so thin as to be trans- parent will conduct if light of proper wavelength falls on the junction layer. The photons received must carry sufficient energy to supply the gap energy and break a covalent bond; we then have a diode in which electron-hole pairs are generated in the depletion region by radiant luminous energy instead of thermal energy. The needed energy for silicon can be obtained with photons in the red and near infrared. An interesting application is made with the gallium arsenide LED, emitting in the red, and the silicon photodiode, sensitive in the red region. The two devices form a photoisolator. General Comments 17 (b) Figure 1.11 (a) The photoisolator, using an LED and a photodiode; (b) photo- diode symbol. as shown in Fig. 1.1 1. The two circuits are isolated from each other except for the light transmitted from the LED to the photodiode. There is no reverse transfer of energy. The reverse saturation current of the junction will still be present when the cell has no illumination and is known as the dark current. Its magnitude should be small compared to the current obtained with useful illumination levels. 7. 15 Capacitance Effects in the pn Diode The pn junction with reverse voltage has a depletion region, acting as an insulator, between the n- and p-conductive regions. The combination acts as a capacitor. The depletion layer thickens with increased voltage as more charges are pulled away from the junction so that the capacitance has an inverse relation with applied voltage. Variation of the reverse voltage can be used to change the capacitance and ranges of 2 to 50 pF arc possible. These diodes are being used as tuning capacitors in high-frequency and TV receiving systems. They are known as varactors or voltage-variable capacitors (VVCs). 1. 16 General Comments Our modern era of solid-state electronics relies on an understanding of atomic structure and electrical conduction processes. We employ the Bohr atom model with a positive nucleus surrounded by electrons in orbits, each having a fixed level of energy. Metals, as good conductors, have a great many free valence electrons to take part in electrical conduction. Conversely, in- sulators hold their charges very lightly and have very few free charges at usual temperatures; therefore, they do not readily conduct. The semiconductors 18 The Semiconductor Diode in the pure or intrinsic state have strong covalent bonding and as a result there arc few free charges available for conduction at room temperature. Impurity additions add free charges in controlled numbers as holes or electrons; with these tailor-made materials we are able to develop the one- way conduction properties of the pn junction. With forward bias the free majority charges are urged across the junc- tion and we have a condition of easy conduction. With reverse bias the mobile charges are withdrawn from the junction region leaving a high- resistance depiction zone. This acts as an insulator. The pn diode is a polarity-controlled switch, with remarkably low voltage required for forward conduction and a high resistance to conduction in the reverse direction. REVIEW QUESTIONS 1.1 What are the parts of an atom? 1.2 How docs a germanium atom differ from an atom of copper or an atom of argon ? 1.3 How many electrons docs an atom of potassium have in its valence shell ? 1.4 Why are silver and copper considered good conductors of electricity? 1.5 What is meant by a free electron in a metal ? 1.6 Describe covalent bonding. 1.7 Describe the mechanism of conduction in intrinsic silicon at room temperature. 1.8 At what temperature docs intrinsic conduction become limiting in silicon electronic devices? What is the equivalent temperature in germanium devices? 1.9 What is a hole in a semiconductor? Why are there no holes in copper? 1.10 Why is a single crystal structure desirable in semiconductor devices? 1.11 What is accomplished in zone refining of semiconductors? 1.12 What is the reason for adding a donor element to a semiconductor? Choose an element that might constitute a donor impurity. 1.13 What is the reason for adding an acceptor element to a semiconductor? Choose a suitable clement for an acceptor impurity. 1.14 What impurities might be used in the two sides of a pn junction ? 1.15 Contrast n- and /?-silicon materials in several ways. 1.16 Why is the permissible operating temperature of// silicon higher than it is for n germanium? 1.17 Explain the development of the depletion region of a junction. 1.18 What is meant by majority and minority charges in n silicon? What is the minority charge in p germanium? 1.19 Explain how a hole moves through a p semiconductor, remembering that the impurity atoms are very far apart. Problems 19 1.20 Where are the minority carriers, and what are they, in a pn junction? 1.21 At a given temperature, /, in germanium is larger than it is in silicon. Why? 1.22 What kind of charges enter each end of the p region in a forward-biased pn junction? 1.23 What is the effect of a forward bias on the depletion region in a pn junction ? 1.24 What is the effect of increasing the reverse voltage on the depletion region of a pn junction? 1.25 What is the cause of the reverse saturation current? 1.26 Why does the reverse saturation current increase with temperature? How fast does ii increase in silicon? 1.27 Why docs the reverse saturation current not vary with reverse voltage? 1.28 What is a photon? 1.29 What is the relation between the energies carried by a photon of red light with wavelength of 7.5 x 10 -7 m and a photon of ultraviolet light with wavelength of 3.75 x IO-'m? 1.30 Explain the phenomenon of avalanching in a Zener diode. 1.31 Explain how a varactor diode acts as a variable capacitance. 1.32 Why is a pn junction sometimes said to be a nonlinear circuit element? 1.33 Why is a diode called a polarity switch? 1.34 The brightness of the LED is dependent on what factor? 1.35 The color of an LED is determined by what factor? PROBLEMS 1.1 Simplify the following quantities with use of the appropriate prefixes on the units: 0.0001 m 9534 x 10"' F 0.0000075 g 12,473 « 1.75 x 10-s mm 0.00475 V 0.0176 x 10"«s 0.0146 A 1.2 What is the energy in electron volts of an electron that has risen through a potential of 3.25 V? 1.3 For a silicon diode with /, = 25 /iA, find the forward current with a voltage of 0.2 V. 1.4 A given diode has /, = 5 x I0~ 6 A; find forward and reverse currents for V = 0.25 V. 1.5 A diode has /, = 5 x 10"' A ; what value of -I V is required to obtain a 75-m A forward current? 1.6 A certain pn diode requires 0.28 V to cause a current of 180 mA in the forward direction. What is the reverse current at 35 V? 20 The Semiconductor Diode 1.7 A Zcncr diode has a breakdown voltage of 20 V. The input to the circuit of Fig. 1 .10(b) is supplied from a 45-V battery and the series resistor R = 2500 Si. What should be the current and power rating of the Zener diode ? 1.8 A Zener diode is rated at V, = 12 V and 6 W power. With V, = 15 V, find the needed series resistance R of Fig. 1.10(b) to keep the diode within power rating. 1.9 A diode conducts 2 fit\ with 10 V applied and the same current with 150 V applied; is it forward- or reverse-biased in each case? What current will it carry when 0.2 V is applied in the forward direction? 1.10 A pn diode carries 50 mA when 0.25 V is applied in the forward direction. What voltage is needed to raise the current to 150 mA? 2 The Diode as Rectifier and Switch The /JH-scmicondiictor diode acts as a switch whose on-off action is con- trolled by the polarity of the applied voltage. The switch has a low resistance and very small voltage drop under forward voltage and a very high resistance under reverse-voltage conditions. Numerous applications depend on this switching property, a major use being the rectification of alternating current for dc power supply. 2. 1 The Ideal Diode Model The semiconductor diode has a voltage-current curve as in Fig. 2.1(a), pre- viously discussed in Sec. 1.11. The straight vertical line at Fig. 2.1(b) is an approximation to the actual curve and represents the ideal diode, assumed to be a closed circuit for a forward voltage and an open circuit for any reverse voltage. This seems a reasonable assumption since the usual forward voltage is less than 1 V and the reverse current is negligibly small at reverse voltages below the Zener level. In effect, we have said that a small forward voltage is required to make a diode conduct but we arc going to call that small voltage zero for ease in calculation. The diode electrodes are called the anode and the cathode. The anode is represented by the arrow of the diode symbol and is internally connected to the p region, while the cathode is the bar of the symbol and is connected to the n region. For forward conduction the anode should be positive and the cathode negative. 21 22 The Diode as Rectifier and Switch - V _l I L 1 2 3 + V - V + V (a) (b) Figure 2.1 (a) pit diode volt-ampere curve; (b) ideal diode curve. 2.2 The Half -Wave Rectifier Circuit On the half cycle of transformer voltage in which the diode anode is positive in Fig. 2.2(a), the diode acts as a closed switch. Voltage v of the transformer, Fig. 2.2(b), is then directly connected to the load and a current /' is present in the circuit as a pulse of half-sine form shown in Fig. 2.2(c). On the next half cycle of transformer voltage the diode anode is negative; the diode is in its reverse condition and acts as an open circuit. No current exists in the load. AC (a) ^dc Figure 2.2 (a) Half-wave rectifier circuit; (b) transformer secondary voltage; (c) load-current pulses. The Half -Wave Rectifier Circuit 23 The successive half-sine pulses of Fig. 2.2(c) all lie above the zero axis and the waves have an average positive value, shown as I ic . The peak of the ac voltage from the transformer is V m and on the conducting half cycle this voltage appears across R. Then the peak of the current pulse is V I 41 K m R ' R With this definition we can determine the dc or average load current as / _ h, - £k «. 031 8K m ~ ItR —R— n (2.1) (2.2) and the dc voltage across the load is K dc -W dc /? = 0.318K„, (2.3) On the reverse half cycle the diode is an open circuit and the entire trans- former voltage appears across the diode. At the peak of the wave this is V m . The insulating depletion layer in the diode has to withstand the peak reverse voltage (PRV) in order to prevent a current. The PRV is an important rating of a diode. For the half-wave circuit PRV=K m = 1.41 V, n (2.4) The average current rating of the diode selected for a particular application must be greater than the expected I ic of Eq. 2.2 and the peak current rating of the diode must be greater than the expected peak current l m of Eq. 2. 1 . Example: A transformer has a rated secondary voltage of 24K rrai . Find the average current, the peak current, the dc voltage across the load resistance of 50 Q, and the needed PRV rating. From our knowledge of sine waves we know that V m = \A\V, m , = 1.41 X 24 = 33.8 V peak Then by Eq. 2.2 By Eq. 2.1 By Eq. 2.3 Using Eq. 2.4 / --^ = ^ : 30- • 2, ^ L = if = ^r ~ omA peak Kic = /ic* - 0.216 X 50 = 10.8 V PRV= V m = 33.8 V peak The Diode as Rectitier and Switch The Bridge Rectifier Circuit 25 2.3 The Full- Wave Rectifier Circuit The full-wave rectifier circuit of Fig. 2.3(a) operates in a more efficient manner by supplying current to the load on both half cycles. The transformer is center- tapped and each half develops a peak voltage V,„. These windings arc op- positely connected to two diodes so that positive voltages are supplied to the diode anodes on alternate half cycles, Fig. 2.3(b), and they transmit current pulses to the load as shown in Fig. 2.3(c). Figure 2.3 (a) Full-wave rectifier circuit; (b) transformer voltage; (c) load- current pulses. In the first half cycle, diode Z), is forward-biased from 7, and conducts a current pulse to the load; diode D z has a reverse voltage from 7* 2 and appears as an open circuit. In the second half cycle, the transformer polarity reverses and diode D 2 is forward-biased from T 2 ; it transfers a current pulse to the load. At this lime diode D, is reverse-biased and open. With the transformer windings and diodes operating independently as two half-wave rectifiers, V m is the peak voltage of each half of the transformer to center tap. The peak current of a diode remains as " R (2.5) The load dc current is the average of two half-sine pulses, however, and is therefore twice the dc value obtained for the half-wave circuit, giving . _ 2(0.318K m ) _ 0.636K„ /dc R - —R— (2.6) The dc load voltage is V ic - I^R = 0.636K m (2.7) The two diodes can be seen as in series across the full secondary voltage of the transformer with a peak voltage of 2V m . One diode is a closed path and the other diode is open at any time. The voltage across the open diode at the peak is the PRV, which is PRV = 2V m (2.8) The full-wave rectifier circuit requires two diodes and a larger center- tapped transformer secondary, from which we obtain twice the dc voltage obtained from the half-wave circuit. However, the required PRV rating for the diodes also doubles. More importantly, the "bumps" of the load current pulses of Fig. 2.3(c) are a better approximation to a "smooth" and steady dc current and are easier to filter into smooth dc current. The use of the full-wave circuit is strongly favored over the half-wave circuit. 2.4 The Bridge Rectifier Circuit At the small cost of two more diodes we can eliminate the center-tapped trans- former and obtain full-wave rectification in the bridge rectifier circuit of Fig. 2.4(a). The transformer has one winding with a peak voltage of V m . On the first half cycle, with terminal A positive, diodes D x and D 3 have forward-voltage conditions and conduct in series as shown in the equivalent circuit at Fig. 2.4(b). Diodes D z and D A are reverse-biased by the transformer voltage in this half cycle and are open circuits. A current pulse having I m = VJR passes downward in the load R. On the next half cycle the transformer voltage reverses and terminal B is positive; diodes D z and D 4 conduct, with the current path as in Fig. 2.4(c). Diodes D, and D } are reverse-biased by the transformer voltage and are open. Another current pulse passes downward in the load R. The current pulses in the load are in the same direction and the load current waveform is that of Fig. 2.3(c) as a full-wave output. The equations for dc current and voltage of Sec. 2.3 apply. Now consider point C in the circuit at Fig. 2.4(c). Point C is effectively connected to A of the transformer because the voltage drop across D z is negligible during conduction. With C at the voltage of A and point E con- nected to B, the open diode D 3 appears connected across the full transformer and has to withstand a peak voltage V m . The diode PRV rating therefore should be V m . Similar reasoning could be applied to each of the other diodes during the appropriate half cycles. 26 The Diode as Rectifier and Switch 5 + c« Djw ^0, I" or *\ E Mc (a) A» (b) (O Figure 2.4 (a) The bridge rectifier circuit; (b) with terminal A positive; (c) with terminal B positive. The bridge rectifier is extensively used because of the lower cost of the transformer and the lower PRV rating for the diodes compared to the center- tapped transformer circuit. 2.5 Measurement of the Ripple in the Rectifier Circuit A battery provides a constant output voltage and is considered an ideal dc voltage supply. However, it is usually more economical to supply dc to electronic equipment from the ac line through rectifier circuits, with batteries used only for portable equipment. As has been shown, the output voltage from rectifier circuits is not steady, and has varying components or ripple superimposed on the average value of the dc voltage, as represented in Fig. 2.5(a). Such variations, remaining from the ac supply as 60- or 120-Hz frequencies, will appear in an amplifier output as "hum" or noise. The amount of ripple in the rectifier circuit output is measured by the The Capacitor Filter 27 (2.9) ripple factor, y (gamma), defined as _ ripple voltage, rms * dc voltage Per cent ripple = 100 y Smaller values of y indicate smoother output voltage, or a closer approach to ideal dc. An ac voltmeter will read the rms value of the ac or ripple component when connected to the rectifier load through a large capacitor to block the dc voltage. The dc voltage can be measured by a dc voltmeter connected across the load, as in Fig. 2.5(b). Wl£ Peak Ripple (a) -W- Load I (b) Figure 2.5 (a) Ripple on a dc voltage; (b) circuit for measurement of ripple percentage. If such measurements are made on the output of the half-wave rectifier circuit, shown in Fig. 2.2(c), the ripple factor would be 1.21, or 121 percent; that is, the ac rms component in the output voltage is 1.21 times as large as the dc voltage. Similarly, the output of the full-wave circuit of Fig. 2.3(c) shows a ripple factor of 0.48 or 48 per cent of the dc voltage. Neither of these ripple figures is sufficiently low for use with most elec- tronic circuits where the expected ripple factor should be in the range of 0.005 to 0.00005, or 0.5 to 0.005 per cent. The latter figure represents a ripple voltage of 0.5 mV superimposed on a dc voltage of 10 V. These requirements show that further smoothing of the rectifier circuit output is needed. It is best to start with full-wave rectification if filtering is to be added, since the original value of ripple is already lower than with the half-wave circuit. 2.6 The Capacitor Filter The availability of capacitors of many microfarads makes the simple capacitor filter of Fig. 2.6(a) desirable as a low cost method of smoothing the rectifier output voltage wave. 28 The Diode as Rectifier and Switch (b) Figure 2.6 (a) Capacitor filler wiih a full-wave rectifier; (b) load and capacitor voltage. Figure 2.6(b) shows the capacitor and load voltage as v c , at the output of a full-wave rectifier circuit. From time 7", to the peak at nil the diode />, is forward-biased by the transformer sine voltage and the capacitor charges through Z), to the peak of the wave at V m . When the transformer voltage falls below V m after ji/2, the diode becomes reverse-biased and conduction stops. If no load resistance were connected to the circuit, the output voltage would remain at a dc level equal to V m . With a load R connected, the capacitor discharges through R and its voltage falls below V m until time T 2 is reached. At that time, diode D 2 becomes forward-biased by an excess of transformer voltage over v c and this diode recharges C to V m for the second half cycle. The fall in v c will be small during the discharge interval from »c/2 to T 2 if C and R are large. This means that the ripple is small. The lime given to capacitor charging will be very short, possibly less than 10° of the cycle. We are able to develop an expression for the ripple of the capacitor filter with a full-wave rectifier as 7 = 0.144 CRf (2.10) where /is the frequency of the supply line. This result introduces the term CRf as a useful design factor. The Capacitor Filter 29 What do we measure with the factor CRf"! We know that the period of the supply sine wave is T — l//and so CRf^^ Thus CRf represents the ratio of the capacitor-load resistance time constant to the period of the sine wave of the supply. In more general terms, CRf measures the ability of the capacitor C to store energy and maintain a voltage near V m until the next diode conduction period occurs to recharge the capac- itor. For low values of ripple factor we want CRf to be large. The result is indicated in Fig. 2.7, plotted for Eq. 2.10. Since the ripple varies inversely with the load resistance, then the ripple increases with load current for the capacitor filter. 0.04 0.03 Q. 0.01 5 10 20 50 100 200 500 CRf Figure 2.7 Full-wave rectifier: ripple and V ic \V m versus CRf for a capacitor filter. Given a specified ripple factor, we have need for 0^44 p yRf (2.11) The dc load voltage is related to the peak of the ac voltage. By study of the wave form in Fig. 2.6(b), we have V* =V m -$A 30 The Diode as Rectifier and Switch where V R is the peak-io-pcak ripple voltage. The dc voltage is obtainable as 1 i i (2.12) ACRf This ratio again involves the design factor CRf and the equation is plotted in Fig. 2.7 against that factor. It shows that for no load (infinite R) the voltage will be equal to K m) as predicted. In Fig. 2.7 we see that CRf> 5 is needed for a ripple less than 0.03, or 3 per cent. With CRf> 5 the dc voltage will be greater than 0.95 K,,. On this upper plateau of the voltage ratio curve, the load (value of R) may change considerably; yet the dc voltage will remain at 90 per cent or higher of the V m value. Thus the filter will give nearly constant dc voltage for varying loads as are encountered with some amplifiers. Example: A full-wave rectifier circuit, operating from a 60-Hz line, sup- plies a load with 200 mA and 30 V dc at full load. What value of C is needed to limit the ripple factor to 0.01 (I per cent ripple)? What should V m be? The ripple will be maximum at full load current, or minimum load resis- tance, which is R = 30 0.200 = 150fi Then, using Eq. 2.1 1 we find C for the filter as 0.144 0.144 C = yRf 0.01 x 150 X 60 - 0.00160 F- 1600 //F The ripple voltage is (30 X y) = 30 x 0.01 = 0.3K rra ,. The design factor is CRf- 0.0016 X 150 X 60 = 14.4 Using Eq. 2.12, 30 1 1 v n -30x 1 1.017 v m * ■ X 14.4 1.017 = 30.5K peak and this is the needed transformer voltage. Figure 2.6(b) indicates that the pulse of current through the diode is of short duration but has a large peak value. In this short interval, the diode must pass the total charge which appears in the load as the average current The n Filter 31 over the half cycle. The peak current requirements of the diode are difficult to calculate because we do not know the length of the diode conduction period. Fortunately we are protected against design inaccuracies by the ability of the diode to withstand large current pulses for a short period of time and by the resistance and reactance introduced into the circuit by the transformer. At initial turn-on of the circuit, however, the filter capacitor is fully dis- charged. This capacitor acts as a short circuit on the transformer and con- ducting diode. The diode will have a surge current rating J s and the initial surge of charging current must be kept below this rating by use of a resistor in series between transformer and each diode. The value of this surge resistor can be calculated from *-* 2.7 The n Filter For applications requiring ripple percentages much less than 1 per cent, the cascaded filtering action of the circuit in Fig. 2.8 is useful. The combination of C„ L, and C 2 is called a n filter because of its similarity to that Greek letter. I D\ I A = Filter and Load -D 1 w 1 i~~T — -'000' » L + fe V m sin u/ • r' H : + *V m sinw/ r R • Di A I 'dc Figure 2.8 Hull-wave rectifier with a n filter. Capacitor C, charges to the peak V m of the applied voltage as does the capacitor C of Sec. 2.6. Therefore we can use what we have already learned about the ripple voltage of the capacitor filter and determine the effect of /. and C 2 in reducing the ripple reaching the load. We shall consider only the full-wave rectifier circuit, as half-wave supply is rarely used with complex filter circuits. Accordingly, the ripple voltage has a frequency twice the line frequency. The effect of the inductor is due to its reactance at double line frequency: X L = 27r(2/I) = AnfL (£2) (2.13) 32 The Diode as Rectifier and Switch The effect of capacitor C 2 on the alternating ripple at the double frequency is 1 1 X c . = (ft) (2.14) c ' 2ti(2/C 2 ) 4tt/C 2 Now C ; will be chosen sufficiently large in capacity that its reactance will be very small with respect to the load resistance R(R ^ I0AT c > for example). Let us calculate the parallel impedance of C\ and R as Using R = lO-Vc, we have JR 1 I X c , jmxi, i But yioi s v^oo « 10 so * ~ \ox c , ** The impedance of a parallel combination of a small capacitive reactance and a large resistance is effectively that of the capacitance only. For the ripple components of the current we have changed the actual circuit of Fig. 2.9(a) to the simpler one at (b). A -—— — ^ L k. Cr. r K ' : (a) A o- Mc (c) Figure 2.9 (a) The n filter ; (b) equivalent circuit for the double-frequency current ; (c) dc equivalent circuit. The n Filter 33 Equation 2.10 was written for the ripple factor across the capacitor filter and can be used for the ripple factor across C, of the n filter in Fig. 2.9, as 0.144 ?■ = (2.15) C x Rf The ripple factor across C : may also be calculated. The voltage-divider action of L and C 2 further reduces the ripple voltage and we can write _ 0-144 Xc. 71 C x RfX L + X Ct But we choose L so that X L > X c , and we can drop X c , in the denominator, giving 0.144 X e . 7z C,Rf X L Substituting for the reactances with Eq. 2. 1 3 and 2. 14 and using the values of the constants, we have (2.16) yi = 9.1 x 10- (2.17) RC x CiLp The ripple factor is inversely proportional to the value of load R. Thus the ripple increases with load current. The inductance and the capacitances have an equal effect on the ripple so that choice of values and their distribution among C,, C 2 , and L is arbitrary. The dc voltage across C, at A, A is given by Eq. 2. 1 2 as V V - AA I - l/(4C,Rf) The inductor may have a dc resistance R c , and this resistance and the load R are connected in series across A, A for the dc current, as shown in Fig. 2.9(c), which is the equivalent circuit for dc. Using resistances R c and R as a voltage divider, we have the dc output voltage of the filter as For small load currents (large R) the dc output voltage of the filter approxi- mates V m if C, is large. Usually C, and C 2 are made large and equal, and L is given a value of 5 or 10 henrys. Example: Filter components might be chosen as C, = 50 /*F, C 2 = 50 fxF, L - 5 H, and rt c - 200 £2, with a load taking 200 mA at 125 V dc. The load resistance is 125 /? = 0.200 = 625Q 34 The Diode as Recti/ier and Switch The Voltage-Doubling Rectifier Circuit 35 The ripple factor is 0.00091 72 ~ 625 x 50 x 10-" x 50 x 10" 6 x 5 x 60 3 = 0.00054 Per cent ripple = 100 y, « 0.054 per cent. This would be a satisfactorily small ripple factor for electronic amplifiers. It represents an mis ripple voltage of 125 x 0.00054 = 0.067 V or 67 mV ripple on the 125-V dc supply. 2.8 The n-R Filter For filters used with rectifiers having small current output, it is often econom- ically desirable to replace the inductor of a n filter with a resistor, as in Fig. 2.10(a). The equivalent dc circuit of Fig. 2. 10(b) is the same as that for the n filter in Fig. 2.9(c) and so the dc output voltage can be calculated by use of Eq. 2. 1 8, repeated here as V*c = 1 + r 4C,Rf A -WAr- K 5 '„. o- A (b) Figure 2.10 (a) The x-R filler circuit; (b) equivalent dc circuit. The resistance of the filter inductor R c usually is in the range of 80 to 400 Q and similar values arc suited to R f in the n-R filter circuit. The ripple factor is found by replacing X L = 4nfL, the reactance of the filter inductor, with R, of the filter circuit and so 0.0114 ,, , n . Since the average power lost in R f is P = l} e R f , the circuit should be employed only when / dc is small to avoid undue power losses and the resul- tant heat dissipation in the equipment. Example: Replacing the 5-H inductor of the example of Sec. 2.7 with its resistance of 100 £2 as R f , we find the ripple factor becomes 0.0114 72 625 x 100 x 50 x 10 6 x 50 x 10" 6 x 60 2 = 0.0202 ripple factor Per cent ripple = 100 y z — 2.02 per cent. This represents a ripple rms voltage of 125 x 0.0202 = 2.53 V The ripple has been increased with the removal of the inductor. The dc voltage will be unchanged, however, since we made R, = R e . 2.9 The Voltage-Doubling Rectifier Circuit A higher value of dc voltage can be obtained from a given transformer by use of the voltage-doubling rectifier circuit, one form of which is shown in Fig. 2.11. With the upper ac terminal positive we have the equivalent circuit of Fig. 2.11(b). With diode D, forward-biased and conducting, diode D z is open. Diode D, charges C, to the peak value of V m , the applied ac wave. On the next half cycle the circuit becomes that at Fig. 2.1 1(c), with B positive. Diode D 2 conducts through C 2 , charging that capacitor to the peak of the ac wave. The capacitor polarities are additive across the dc output terminals; at no load this voltage is equal to the double-peak value of the ac input wave. The diodes conduct high peak currents for short intervals and C, and C 2 must be of high capacitance to maintain the dc voltage over the nonconducting intervals of the diodes and to give a low ripple percentage. The doubler circuit is useful for high dc voltages because the transformer has a lower total voltage and the transformer insulation requirements are reduced in comparison to other circuits. Performance data are presented in Fig. 2.12. Figure 2.1 1 (a) A voltage-doubler rectifier circuit; (b) and (c) equivalent circuits on alternate half-waves. 2.0 1.8 1.6 • *M 1.4 1.2 - \ ' ' MM - 1 -i— - - - ' / Ac \ Ripp le - / i i .1111 1 J— iTm - 0.08 0.06 0.02 10 20 CRf 50 100 200 Figure 2.12 The voltage-doubler rectifier circuit performance. 36 Rectifying AC Voltmeters 37 The principles used in the voltage-doubling circuit may be extended to obtain still higher voltages. Such voltage multipliers use a ladder arrangement to increase the output dc voltage but applications are limited because of high ripple percentage with small output currents. 2.10 Rectifying AC Voltmeters Instruments for the measurement of ac cannot employ iron in their field struc- tures because the action of the iron varies with frequency and such variation will introduce errors with varying frequency or waveform. With only air in the magnetic circuits, the ac instruments operate at low field-flux densities and must have large currents in the moving coils to give useful deflections. Permanent magnet-moving coil (PMMC) instruments for dc measurement derive their field flux from permanent magnets, however, and a smaller current can be measured than is possible with ac instruments. Therefore, we often combine diodes with PMMC instruments, rectifying the small ac currents and performing their measurement with low-current dc instruments. The bridge rectifier circuit of Fig. 2. 13(a) is used, leading to ac voltmeters o w- AC if (a) (b) Figure 2.13 (a) Full-wave average-reading meter; (b) peak-reading ac voltmeter. that may have internal resistances of 2000 £2 per V of scale or give full-scale deflection with a current of only 0.5 mA. The dc instrument coil is supplied with full-wave rectified current pulses and the deflection is proportional to the average or dc value of these pulses. From Eq. 2.6 for the full-wave rectifier circuit, / dc = 0.6361* = 0.636 F + Ro (2.21) 38 The Diode as Rectifier and Switch where V m = peak value of the applied ac voltage R m = series multiplying resistance of the instrument R =-■ the resistance of the instrument movement We assume that ideal diodes are being used. Inverting the equation above we have K m = 0.636 which is the peak value of the ac voltage applied to the instrument for a given dc instrument current. To determine the rms value of the ac voltage at the instrument terminals, we multiply by l/^/~T — 0.707 and have 0.707K„= W&iR. RoV, Jc 0.636' - l.\\(R„-R B )I ac (2.22) where /,,,. is the current measured by the deflecting coil of the dc instrument. The scale introduces the factor 1.1 1, which is appropriate only for a sine waveform from which we obtained the factors 0.636 = 2/n and 0.707 = \/*J~2 . If the input wave is not a sinusoid, the instrument indication will be in error. Another form of rectifying voltmeter appears in Fig. 2.12(b) and employs a half-wave diode with a capacitive filter. The voltage applied to R m and the instrument is equal to the peak of the ac wave. The scale is calibrated to read in rms values of that wave and includes the 0.707 factor. Again, errors arise if the applied waveform is not sinusoidal. 2.11 Diode Wave Clippers The polarity-switching property of the diode permits its use in simple clipper circuits to remove parts of waveforms. The circuits employ a diode, a resistor, and often a battery or voltage source. The output waveform can be clipped at different levels, dependent on the diode connection and the battery polarity and potential. Basic forms include series and parallel diodes and biased and unbiased circuits. The circuit of Fig. 2.14(a) employs a parallel diode and scries resistor R, connected to clip off all positive voltages; essentially the circuit is a half- wave rectifier. When point A is positive to ground, the diode is forward- biased and appears as a short circuit, through use of the ideal diode model. For v, > 0, the state of the circuit is shown in Fig. 2.14(b) and v„ = 0. For v, < 0, the diode is reverse-biased and open and the state of the circuit be- comes that of Fig. 2.14(c). For a sine-wave input the output wave is that at Diode Wave Clippers 39 Fig. 2.14(e). Resistor R should be large with respect to the diode resistance; 10,000 Q is suitable for most diodes. A biased parallel clipper is shown in Fig. 2.15(a), with clipping of all posi- tive voltages above I 10 V. With v, < + 10, point A is negative to the diode n A A A r\ . A __o R "i W- O (a) -WW- R Vi>0 « o =0 (b) v,<0 ^vvW- R "o="l T (c) (d) 2ir Figure 2.14 (a) Parallel diode positive clipper; (b) circuit of (a) for «/ > 0; (c) circuit of (a) for ut < 0; (d) input sine voltage; (e) clipped sine voltage. o \AAAi i h o R ! :d + i°:e °" o VWV A v,< 10 vW— — » o R * Open v„ = 10 ■=- o W/v- R v, > 10 '« !')■=- * 10 (;■) (b) (cl (d) + 10V (e) Figure 2.15 (a) Clipping at -f 10 V; (b) for v, < 10; (c) for * > 10; (d) and (e) waveforms. 40 The Diode as Rectifier and Switch cathode al -f 10 V, the diode is open, and the circuit is that of Fig. 2.15(b). The input voltage is transmitted to the output as ?•„. With v, > +10 V, the diode closes and the circuit becomes that at Fig. 2. 1 5(c), giving 1 V across the output. For sine-wave input the output wave appears at Fig. 2.15(e). In analysis of the circuit to determine the output waveform, the several circuits should be drawn for each voltage state, noting that switching between Scries o 1* *VW (a) *V. (b) Parallel ""~innr (c) Figure 2.16 Clipper circuits, with sine-wave inputs. o vwv R — o o— Dy. — o O \MAr R [ — o »T "i h "o o— "J —o o VWV- R I — o /)? «/ "o o^ 4, —o o VWV— • « :crmf (a) OAA /.. 'i (h) n n . 'n 'i Figure 2.17 (a) Sine wave clipped lo form a square wave; (b) reshaping of dis- torted pulses by clipping. Diode Clampers 41 the circuits occurs at V B in each case. Series and parallel forms of clipping circuits are compared in Fig. 2.16. Reversal of diode and battery polarities will rotate the waveforms about the zero voltage axis. Several applications of clipper circuits are shown in Fig. 2. 17. At (a) is a double-diode clipper that can be used to form approximate square waves from a sine-wave input. When followed by amplification and a second clipping operation the rise time of the pulses can be made quite short. At Fig. 2.17(b) we have the process of restoration of distorted pulses by clipping below the noise level. 2. 12 Diode Clampers A clamping circuit employs a diode, a resistor, and a capacitor and will place a wave on a desired dc axis. For instance, Fig. 2.18(a) shows a circuit whereby the unsymmetrical input pulse at (b) is clamped with its positive peaks at zero in (c). The RC values of the circuit should be chosen so that the time constant is at least five times the period of the input wave; that is, with the period at \/f, then RC > 5/f. When the wave goes to +5V at t a , the capacitor charges -K- »< D v„ + 5 n (a) U '0 '1 '2 u '0 '1 '2 - 10 - 15 (b) (O -?r~ i + 5 ^ D "0 = 1 '0<'<'l (d) T_l 10— D °a i>„= 15 l\<K'2 (e) Figure 2.18 (a) Diode clamp; (b) input pulse wave; (c) output clamped at V; (d) and (c) circuits during operation. 42 The Diode as Rectifier and Switch quickly through the diode to -I 5 V and we have the circuit condition of Fig. 2. 18(c) that exists tor,. At/, the input drops to - 10 V, and with the capacitor charged to -f 5 V the diode voltage is —15 V and it opens, leading to the circuit at Fig. 2. 1 8(d) and - 1 5-V output. The output wave at Fig. 2.18(c) shows that the positive peak is now clamped aX V and the pulse swings down to —15 V. The positive peaks may be clamped at other dc levels by introducing a voltage V„ in series with the diode. 2.13 Review The ideal diode model is useful in circuit analysis because of its simplicity; it employs the concept of zero forward-voltage drop when the diode anode is positive to the cathode and zero current with reversed polarity. An actual semiconductor diode provides a good approximation to the performance of the ideal diode in most applications. The full-wave rectifier circuit is an important application of the polarity- switching diode. The dc quantities in a resistance load are /dc = 2V m . V*c = IV. The ripple, at 48 per cent of the dc voltage, is too large for a dc supply in most electronic circuits. The bridge rectifier circuit reduces the needed transformer voltage by one- half. This eliminates the relatively high cost of a center-tapped winding at the expense of adding two additional diodes. It is now a much-used circuit form. Ripple can be reduced by the addition of a filter capacitor across the load. The dc voltage will approach V m of the ac wave applied. The parameter CRf, with/as the supply frequency, is useful as a performance factor. The ripple reduction improves with increasing CRf values. Further reduction of ripple voltage is possible by use of the n filter but this adds an expensive and bulky inductor. Replacement of the inductor with a resistance saves cost, space, and weight but sacrifices dc voltage if the ripple is to be small. Filter circuits are compared in Table 2.1, several employ an input capaci- tor of many microfarads. This seems a better choice for modern small equip- ment than filter circuits using inductor input since the capacitor is lighter, cheaper, and smaller per unit of filtering effect than is the iron-cored inductor. A capacitor input filter also provides output voltages near V m and gives good control of that voltage if sufficient filter capacitance is used (large CRf). Thus these circuits make efficient use of the transformer. Review Questions 43 TABLE 2.1 Filter-Circuit Comparison (Full-Wave Rectifier) >"dc Ripple No filter Capacitor filter n filler n-R filler 2K. n I I 4CRJ I \R I R c ) 4C,Rf K 1 + \R I R f ) 0.485 0.144 TRf 0.00091 RC,C z Lf> 0.0114 XR/CCtf* REVIEW QUESTIONS 2.1 What is an ideal diode? 2.2 A sine wave of voltage is applied to an ideal diode. At what angles in the wave does the diode switch on and off? 2.3 The secondary voltage or a transformer for a half-wave circuit is 35K Im ,. What should the voltage rating of a transformer for a full-wave center-tap rectifier be, assuming equal dc voltage output from the rectifier? 2.4 Define (a) Peak reverse voltage (b) Average current (c) Maximum current (d) Ripple 2.5 Name several advantages of full-wave rectification over half-wave rectification. 2.6 For rectifiers with resistance loads and 60-Hz supply, what is the frequency of the ripple component in the load voltage of (a) Half-wave rectifier (b) Center-tap circuit (c) A bridge rectifier 2.7 What is the effect of a defective diode that is continuously open on the output voltage and the ripple of a full-wave rectifier? 2.8 What are several advantages of the bridge rectifier circuit over the full-wave center-tap circuit? 2.9 Name at least one disadvantage of the bridge rectifier over the full-wave center- tap circuit. 2.10 What is the purpose of a filter circuit? How does it accomplish this purpose? 2.11 Why do diodes carry short current pulses when a capacitor filter is used? 44 The Diode as Rectifier and Switch 2.12 What components of the diode current pass through the load in a capacitor filter circuit? 2.13 Why does the voltage output of a capacitor filter approach V n in magnitude? 2.14 Name an advantage of a n filter over a capacitor filter. Name a disadvantage. 2.15 What is the effect of the resistance of the inductor winding in a n filter? 2.16 Name several disadvantages of filters employing inductors. 2.17 Under what conditions do we use a n-R filter? 2.18 What is the relation of the maximum voltage rating for the filter capacitors to the rms voltage of the transformer with a bridge rectifier circuit? 2.19 What is an advantage of a voltage-doubler circuit ? 2.20 Is the voltage-doubler circuit of Fig. 2.11 a half-wave or a full-wave circuit? 2.21 If a PMMC instrument measures the load voltage of a half-wave rectifier, what is the component measured ? 2.22 The diodes of the bridge rectifier of Fig. 2.13 are not ideal. How would you alter Eq. 2.22 to include the effective diode resistance? 2.23 A dc voltmeter reads 680 V across the output of a voltage-doubler rectifier, at no load. What would an rms ac voltmeter read across the transformer secondary that supplies the rectifier? PROBLEMS 2.1 Determine the dc voltage obtained by half-wave rectification of an ac wave of 180-V rms. 2.2 What PRV rating should the diode of Problem 2.1 have? 2.3 A half-wave rectifier circuit supplies 100 mA dc to a 500 Q load. Find the dc load voltage, the PRV rating for the diode, and the rms rated voltage of the transformer supplying the rectifier. 2.4 Find the dc load voltage obtained from a full-wave rectifier in which the trans- former supplies a peak voltage of 150 V on each side of the center tap. 2.5 The dc output voltage of a full-wave rectifier is 120 V. What is the needed rms voltage rating for each half of the center-tapped transformer? What is the peak ac voltage rating for the full transformer secondary? 2.6 A center-tapped transformer supplies the diodes of a full-wave rectifier giving a dc output across the load of 180 V. What PRV rating should be used for the diodes? 2.7 Determine the needed PRV rating for a diode in a bridge rectifier supplying 80 V dc to a load. 2.8 A full-wave rectifier has 125 V dc output to a resistance load. What is the rms value of the ripple voltage? 2.9 Calculate the needed transformer voltages to supply a load at 50 V dc, from (a) A half-wave rectifier circuit Problems 45 (b) A center-tapped full-wave circuit (c) A bridge rectifier circuit (d) Determine the diode PRV ratings for each case. 2.10 A rectifier output following a filter has an rms ripple voltage of 1.72 V, with a dc load voltage of 90 V. What is the ripple factor? 2.1 1 A bridge rectifier supplies a resistance load with 2 A dc at 20 V dc. What trans- former voltage is needed (rms)? 2.12 A full-wave rectifier is supplied with an rms voltage of 80 V, 60 Hz on each side of the transformer center tap. A 10-//F capacitor is used as a filter and the load takes 50 mA dc. What dc voltage is being obtained at the load? 2.13 A transformer with 250-0-250 V rms, 60- Hz secondary supplies a full-wave rectifier having a load of 1500 CI. Determine the dc load voltage and current, the PRV rating needed for the diodes, and the average current of each diode. Draw the circuit. 2.14 A transformer with 250 V rms, 60-Hz secondary supplies a bridge rectifier having a dc load of 1500 SI. Determine the dc load voltage and current, the PRV rating of the diodes, and the average current in each diode. 2.15 A silicon diode is used in a half-wave rectifier circuit operating from a 20 V rms, 60-Hz transformer. The load is a 10-O. resistance. What is the peak diode cur- rent? What is the average load current? What should the PRV rating of the diode be? What is the rms value of the ripple voltage? 2.16 A full-wave rectifier is supplied at 60 Hz by a transformer with a center tap. With a 400-fiF filter capacitor, calculate (a) The ripple (b) The rms ripple voltage (c) The rms voltage rating each side of center tap for the transformer, for a load taking 400 mA at 50 V dc. 2.17 Operating from a 60-Hz line, a transformer supplies a peak voltage of 140 V each side of the center tap to a full-wave rectifier. The capacitor filter has a dc output voltage of 120 V and a dc current of 50 mA. Calculate the value of C used in the filter. 2.18 An RC filter supplies 80 V dc with 1.5 per cent ripple. What is the rms ripple voltage? 2.19 A rectifier transformer operates at 60 Hz and supplies a full-wave rectifier with a capacitor filter of 100 //F. The load takes 200 mA at 50 V dc. (a) What is the no-load (R very large) output voltage? (b) What should be the rms voltage rating of the transformer, measured to center tap? (c) What is the per cent of ripple at full load? 2.20 A 60-Hz transformer having a 40-0-40 V rms secondary supplies a full-wave rectifier circuit. The load is 100 Q. with a filter capacitor of 3000 //F. Find (a) The dc load voltage (b) The rms ripple voltage across the load (c) The PRV rating for the diodes. 46 The Diode as Rectifier and Switch 2.21 A transformer on a 60-Hz line supplies a bridge rectifier. A capacitor filter and a load of 24 SI gives a ripple of 1 .2 per cent at a dc voltage of 40 V. (a) What rms transformer voltage is needed ? (b) What capacitance is needed for the filter? (c) What should be the voltage rating for the filter capacitance? 2.22 With a full-wave rectifier at 60 Hz, a n filter supplies 154 V dc to a load. With an ac voltmeter having a large series capacitor, the voltage measured across the load is 127 mV rms. (a) What is the ripple factor? (b) If the dc load current is 0.250 A, what value of C= C, — Ci is being used in the filter? L 10 H. 2.23 Determine the ripple factor for a bridge rectifier circuit at 60 Hz with a n filter having C, C : - 100 fiF, L = 7.5 H, and a load current of 500 mA at 60 V dc. 2.24 Determine the ripple factor for a bridge rectifier circuit at 60 Hz with a capac- itor filter of 2000 //F and a load taking 500 mA at 6 V dc. 2.25 The circuit of Fig. 2.19 uses a transformer with 120-0-120 V im , secondary. (a) What is the magnitude and polarity of voltage at A with no load? (b) Find the same quantities at B, also with no load. (c) If the load at Sis 1000 £2, what is the ripple percent there, 60-Hz supply? Figure 2.19 2.26 What is the dc voltage available at no load from a voltagc-doubler circuit supplied by a source of 120 V, 60 Hz, at no load? 2.27 A bridge rectifier operating at 60 Hz is to supply 1 A at 35 V, with a ripple less than 0.5 V rms. Specify C and the transformer voltage rating, the average diode current rating, and the PRV rating. 2.28 In Problem 2.27, what surge protection resistor should be used if the diode surge current rating is 30 times the average current? Problems 47 2.29 A bridge rectifier with n filter uses two 40-//F capacitors and one 10-H inductor of zero resistance. The transformer voltage is 300 V rms, 60 Hz and the dc load current is 150 mA. Find the dc output voltage and the ripple. 2.30 The waveform of Fig. 2.20 is applied to the ammeter shown at Fig. 2.20(b), where M is a PMMC average reading instrument with 1-mA full-scale reading. If the diode is ideal, what does the meter read if its resistance is 9000 Q. + l(K) V -« — ►- 10 nu 50 V 50 ins 10 ins 100 ms (a) (b) Figure 2.20 3 Models for Circuits Transistors and tubes arc called active devices because they convert energy from dc to ac at signal frequencies. Simple models are needed for the active devices, that can be used in circuit analysis along with resistors, capac- itors, and inductors. With such models we can design our electronic systems on paper and determine how ihey should be operated for best performance. Breadboarding and checking of the circuits can follow in the laboratory. Without preliminary calculation with models, ihe laboratory work becomes an exercise in frustration of the cut-and-try variety. Fortunately, those who work with electrical circuits have shown us how to develop models for circuits that contain energy sources, and are active. While seemingly rather abstract, we can use these methods to replace actual active devices with a simple circuit model that performs in an equivalent manner. 3. 1 The Black Box Concept Consider a device as simple as a relay. It has an input pair of terminals or an input port and an output pair of terminals or an output port. If we apply a proper voltage (or signal) to the input port, we discover that a connection appears across the output port. If we know what happens at the output port for every input condition, we do not need to know the internal design to utilize the relay in a control system. The relay box might be painted black 48 The Black Box Concept 49 to hide its internal details, with just the ports exposed. Then the box of Fig. 3.1(a) might represent the relay as a two-port network. A simpler one-port network is shown at Fig. 3.1(b). lo- lo- Nelwork -02 -02 (a) (b) Figure 3.1 (a) A two-pon network ; (b) one-port network. A great many of our electrical devices can be thought of as "black boxes" with one or two ports. We are able to apply them because of our knowledge of the electrical performance at the ports; we do not have to know what happens internally. For instance, we buy transistors by calling for a type number that assures us that the output will respond to the input in a certain way. We need not ask how the transistor is built internally; thus we buy transistors as black boxes. • We can study the performance of the one-port box of Fig. 3.2(a) by means of the current and voltage at the port. The values obtained indicate the response of the box to a connected source or load. Now, consider the second box in Fig. 3.2(b). If for every value of applied voltage K, = V z we I o- io- Network A I o- 1 °- Network B Figure 3.2 Two one-port electrical networks. find that current /, ■■ / 2 , we would conclude that the electrical networks inside the boxes were the same in external performance. One box could be replaced with the other without noticing any difference at the ports and we would say that the boxes are equivalent. We need not know anything about the internal operation or connections of the boxes. We conclude that a circuit is equivalent to a second circuit if the second circuit can be substituted for the first without change in the currents and voltages appearing at the ports. Now, if we can devise a circuit model that operates at input and output ports the same as does a transistor, then we can use that circuit model in place of the actual transistor. 50 Models lor Circuits I In the networks of Fig. 3.1, the conventional current and voltage polar- ities are indicated. The currents moving inward are made positive at both ports of the two port so that a network can be reversed or changed end-for- end without altering an analysis. 3.2 Active One-Port Models : the Voltage-Source Circuit Suppose that we connect a voltmeter at the port of Fig. 3.3(a), and discover that a voltage K, is present. We conclude that the box contains a source of electrical energy and houses an active network. It would be useful to deter- mine a circuit equivalent for this box. |o- + lc~ Active Network (») (b) Figure 3.3 (a) An active one-port network; (b) the series form of equivalent circuit. We know that some internal voltage source is present and we speculate that the source might have some associated impedance. We then have two unknowns, a source V and an impedance Z', that can only be connected in two ways— in series or in parallel. We might start with assumption of the series form at Fig. 3.3(b). We need two algebraic equations to determine the two unknown quantities; these equations might be obtained by connect- ing two arbitrary loads at the port and measuring the resultant voltage and current. Probably the simplest loads we can find are an open circuit and a short circuit; the latter will cause no damage as long as we work only on paper! We measure the voltage at the port of Fig. 3.3(a) without load and call that value V, = V,,,.. Using the circuit of Fig. 3.3(b) and an open-circuit load, we measure V at the port. For equivalence of the two boxes we must have V,. = V (3.1) Now apply a short circuit to port 1,1 in Fig. 3.3(a) and we measure a current I, = I ]C ; similarly with a short circuit on the port of (b) we measure Ii = I'|. For equivalence of the two boxes our second condition is I.c - r, (3.2) Active One-Port Models: the Current-Source Circuit 51 With the short circuit in place across the l,l terminals of Fig. 3.3(b), we can write a circuit equation V ZT - Substitution of the necessary conditions for equivalence as given by Eq. 3. 1 and 3.2, we have V M Z'I, C - and (3.3) z 77 Therefore we have in Fig. 3.3(b) an equivalent circuit for the box at (a) if V - V oc (3.4) (3.5) Z'=^c The equivalent circuit includes a voltage generator V equal to the open- circuit voltage at the port of the original network and a series impedance Z' determined from the open-circuit voltage and the short circuit current. This circuit in Fig. 3.3(b) can be made equivalent to any one-port network and is known as the voltage-source equivalent circuit or the Thevenin equivalent circuit. 3.3 Active One-Port Models: the Current-Source Circuit Let us place a load Z L at the output port of the voltage-source equivalent circuit in Fig. 3.4(a). A voltage equation written around the loop is V - Z'\ L - \ L = (3.6) Division by Z' and rearrangement of the terms gives V'_, . Vl T ~ h + Z (a) (b) Figure 3.4 (a)Thcvcnin's scries equivalent circuit and load; (b) Norton's parallel equivalent circuit and load. 62 Models lor Circuits But V'/Z' = I,. by Eq. 3.4 and 3.5 and we can call V t /Z' = I,, so that the equation above becomes I* - h + Ia (3.7) This equation is that of a current summation at point A for the circuit in Fig. 3.4(b). The circuit in the box consists of a current generator I„ and a parallel impedance Z', as derived for the voltage-source circuit. The circuit in Fig. 3.4(b) was derived from the voltage-source circuit at (a) and so we have another active one-port equivalent circuit, the current- source equivalent or the Norton equivalent circuit. By mathematics we have found the parallel form of circuit that we originally stated as possible. Since the voltage-source circuit and the current-source circuit are equiva- lent, transference from one form to the other is often used in circuit sim- plification. (a) (b) Figure 3.5 Circuits for the example. Example: We find that with open circuit at 1,1 of a box the voltage is 5.2 V. With a load of 2 Q connected to those terminals the current is 1.7 A. Determine the circuit values for active one-port equivalent circuits. Since we have two unknowns in the box, we need two equations for solu- tion. From the problem data, V M - V - 5.2 V is one relation. The second relation comes from the equivalent circuit in Fig. 3.4(a) as V - IT -IZ L = With / given as 1 .7 A for Z L -= 2 £2 and V = 5.2 V, we have 5.2- 1.7Z' - 1.7 x 2- 1.7Z' = 5.2-3.4= 1.8 z' = |^= i.06 n Therefore our voltage source should be that in Fig. 3.5(a), with V" = 5.2 V andZ' - 1.06 SI. 53 Maximum Power Output We can calculate 7, c as ^ = F = m- 4 - 9IA and the current-source circuit is that in Fig. 3.5(b) with I K = 4.91 A and Z'= 1.06 ft. 3.4 Maximum Power Output Many of our electronic power sources, such as microphones, are expensive and develop very little power output. For these generators we try to maxi- mize the power output per unit of investment by operating such sources under conditions that will give the maximum power output to a load. The voltage source in Fig. 3.6(a) represents any active one-port circuit; for simplicity we assume that the load is resistive and Z' — R'. If we use an open-circuit load at 1,1, the output current will be zero and there will be zero power output. Likewise, if we use a short-circuit load at 1,1, the output resistance is zero and there will be zero power output. These are the limits (a) 0.5 Im B § O 0.3 b B E & 0.2 0.1 0.2 0.5 1.0 2 5 10 R L /R' (b) figure 3.6 (a) A voltage source and load R L : (b) output power to the load versus RlIR: — i — i — i>-n i i i i i i r "J i i i i : i l. _i_ i ii i. 54 Models lor Circuits for the load and if we experimentally try other load values, the curve in Fig. 3.6(b) develops. This curve shows that the maximum power is delivered from the active generator circuit at 1,1 when R L - R' (3.8) This is the condition of a matched resistive loud. With the same current in R L and R\ the load power is P L — l l R L and the internal power loss is P a = PR'. With R L = /?', these powers are maximum and equal. The power transferred to the load is only 50 per cent of the total power generated, however, or the output efficiency is 50 per cent. Needless to say, industrial and domestic power systems cannot afford to waste one- half of their output in the generating plant and do not operate with matched loads; such systems use loads much higher than the matching value to achieve high output efficiency. Example: For the voltage-source equivalent circuit in Fig. 3.5(a) the current / is R' I R L and for the matched load we have R' — R L so that 5.2 5.2 W 2 X 1.06 2.12 = 2.45 A The power delivered to the matched load is P L -- PR L - 2.45 2 X 1.06 = 6.37 W The total power generated is P G - P(R' - R L ) = 2.45* X 2.12 = 12.73 W and the efficiency of delivery of power to the load is 50 per cent. 3.5 The Two-Port Network We also make frequent use of a transmission type of network in which there arc input and output pairs of terminals, as for the two-port network sym- bolized by the black box in Fig. 3.7(a). There are four undetermined quan- tities at the ports of this network, namely V u /,, V 2 , and l 2 . Consequently, if we are to find an equivalent circuit for any network in the box, we shall need four measured parameters. We can relate four parameters with four terminal voltages and currents by a pair of equations, and electronic usage has shown these desirable: V, = h,I, + h,V 1 (3.9) h = Vi + h - y i (3.10) The Two -Port Network 55 1 o- I o- (a) Qv. ii v-\ <b> -o2 hZ v * -o2 Figure 3.7 (a) A two-port black box; (b) the //-parameter equivalent circuit. where these are alternating voltages and currents. The subscripts of the h parameters are a standard usage. Borrowing from the method already used for the one-port circuit, we can take measurements at the ports with open- and short-circuit loads and choose the internal elements of the equivalent circuit to yield the same ter- minal measurements. With a short circuit at 2,2 we have V 2 — and, inserting that condition in Eq. 3.9 and 3.10, we find V t - v, h - v. and so we are able to define /;, and h, by the following measurements made at the 1,1 terminals: *-a .•2 ihorl = short-circuit input resistance (3.11) h f = -f-\ = short-circuit forward current gain (3.12) ' I J2.2 Ihotl Taking measurements at the 2,2 port with an open circuit at the 1,1 port means that /, = and using that condition in Eq. 3.9 and 3.10, we have v, = hjr, h - V. Then we define It, and h by the following measurements made at the 2,2 56 Models for Circuits terminals: V 1 h, = Tr\ — open-circuit reverse voltage gain (3.13) " 2 Jl. 1 open h„ = rr = open-circuit reciprocal output resistance (3.14) ' aJli I open The defined // parameters include an input resistance, the reciprocal of the output resistance, and two dimensionless ratios: consequently, the /; coefficients are called the hybrid parameters. With alternating voltages and currents the parameters /?, and //„ should be stated in units of impedance and reciprocal impedance but they are usu- ally considered as resistive. 3.6 The h-Parameter Equivalent Circuit With h parameters corresponding to the measurements, Eq. 3.9 and 3.10 will act as a mathematical equivalent for any two-port network. Our remain- ing step is to find an actual circuit that can be used to represent that original box. The hybrid equations were set up as V t - V, + h,V z (3.15) h = V. + h V z (3.16) Equation 3.15 appears as a sum of voltage terms and, with K, at the port, the right-hand terms represent the sum of voltages inside the box. The h,I, term is a resistance voltage drop and is shown as due to //, at port 1,1 in Fig. 3.7(b). The second term represents a controlled voltage generator, whose output is dependent on the voltage at the output port. The parameter h, is the constant of proportionality. Equation 3.15 is simulated by the series circuit at port 1 . Equation 3.16 states the sum of currents at A in Fig. 3.7(b). Current / 2 enters at the port and /i K 2 leaves through resistance \/h . The second term is a leaving current due to a controlled current generator, whose output cur- rent is proportional to the input current at 1,1; Ay is the constant of propor- tionality. We have the circuit connected to port 2 representing Eq. 3.16. Figure 3.7(b) is an equivalent circuit for any two-port network, defined in h parameters. It should be noted that it comprises two one-port equiva- lents, with a voltage-source equivalent circuit appearing in the input loop and a current-source circuit appearing in the output loop. Example: Find the // parameters for the circuit in Fig. 3.8(a), and draw the equivalent circuit. A short circuit at 2,2 connects the 12- and I5-Q resistors in parallel and The h-Parameter Equivalent Circuit 67 1 n— i i Sft A 12ft 1 — o •> 1 v^- + I + *i i I i ! 1 1 I .1512 . -o 7 i °— 1 v i. (a) ly — l°- L. •II.7J2 ^lp.5S6 V 2 0.556 f> ' -02 0.037 7J (b) Figure 3.8 Circuits for example. the input resistance at 1,1 is due to 5 Q plus the parallel value, that is, (s.c.) fc-^-S + gf^-HJO With the short circuit at 2,2, current /, divides at A. Then 12 x 15 y M - /. Also We can then write 12+ 15 _/ _ y M ... i »S 2 12 ~ ' 12 -F 15 (s.c.) *, = £= -^=-0.556 With an open circuit at 1,1 there is no current in the 5-Q resistor and so the output resistance measured at 2,2 is r = 12+ 15 = 27 Q. (o.c.) A. = — = i= = 0.037 mho To 2.1 68 Models lor Circuits Still with an open circuit at 1,1, the voltage across the I5-Q resistor is V t . Then '*"" 12 | 15 V, = 15/, = 15K, 12+ 15 and so (o.c.) h, = £ = £ = 0.556 The circuit parameters are entered on the circuit diagram in Fig. 3.8(b). 3.7 Power in Decibels In the communications field it is usual to measure power gain in decibels. Devised by the telephone industry and originally named the bel for Alexander Graham Bell, the decibel is one-tenth as large and of a more useful magnitude. The decibel (dB) is defined as number of dB - 10 log^ * i (3.17) where log indicates a logarithm to the base 10. The ear hears sound intensities on a logarithmic intensity scale and since many amplifiers supply an audio output, the use of a logarithmic power scale becomes reasonable and convenient. In fact, it was intended that a 1-dB step be the minimum intensity change that is just noticeable by the human ear but experiment has found that the minimum noticeable intensity change is nearer 2.5 dB. To illustrate the use of the decibel, assume the output of an amplifier under one condition is 3.5 W with an input of 0.12 W. The power gain, measured in decibels, is dB= 10 log ^ = 10 log 29. 17 = 10 X 1.46 = 14.6-dB power gain If the amplifier output is increased to 7.0 W, then the decibel gain is dB= I0logi^= 10 log 58.3 = 10 x 1.76 = 17.6-dB power gain Doubling of the power gain is shown by a 3-d B change. An amplifier with a power gain of 90 has dB- 10 logy -10 x 1.95- 19.5 dB Power in Decibels 59 and the amplifier has a gain of 19.5 dB. It is followed by a second amplifier with a power gain of 250 and dB - 10 lqgyL= 10 x 2.40 = 24dB The overall power gain is 90 x 250 = 22,500 and in decibels this is dB= 10 log 22,500- 10 log (2.25 x I0 4 ) = 10 (log 2.25 I 4)- 10(0.352 • 4) = 43.5 But 43.5 ■= 19.5 — 24 and we see that the overall gain of amplifiers in cascade can be calculated by adding the respective gains in decibels as overall gain, dB - dB, + dB, + dB 3 + . . . (3.18) While defined as a power ratio, the decibel is also used for absolute power measurement when a reference or zero level is stated for P x . A variety of zero levels has been used; the one now commonly employed is 0.00 1 W (1 mW). Consequently we can state the output level of the amplifier with 7.0- W output as 7 10 log 0.001 = 10 log (7 x 10 3 ) - 10(log7 + 3) = 10(0.84 + 3) - 38.4 dB above 1 mW This unit is sometimes given as dBm (decibel referred to one milliwatt), to indicate the 1-mW zero level. The amplifier with 3.5-W output has decibel output 10 log 3.5 0.001 - 10 log (3.5 x I0 3 ) = 10(0.54 + 3) - 35.4 dB above 1 mW Taking the difference of the 7.0- W output and the 3.5-W output, 38.4 - 35.4 = 3.0 dB which was the original difference in the amplifier outputs. If this figure had been negative, a loss would have been indicated. We may wish to find the dBm of a microphone with 0.0000062-W out- put. With zero level at 0.001 W, we write dBm - 10 log kffjffi 62 - 10 log 0.0062 Obtaining the logarithm of a number less than unity need pose no problems. so Models for Circuits Problems 61 Using scientific notation we can employ our regular methods as dBm = 10 log (6.2 x 10 3 ) = 10 (log 6.2 - 3) - 10(0.792-3)= -22.1 and the result is staled as 22.1 dB below 1 mW. Power is given by P = V 2 jR or PR. The decibel power gain can be found through use of cither of these expressions. For instance, If R z = R„ then But we have gain in dB- lOlogp^ gain in dB = 10 log (j^V and we find that the gain can be written gain in dB - 20 log ^ (3.19) We commonly calculate amplifier gains by use of Eq. 3.19 as a voltage ratio or as the current ratio gain in dB - 20 log ^ 'i (3.20) 3.8 Comments The concept of an equivalent circuit, equal in terminal voltages and currents to any actual network of unknown internal elements and connections, is a very useful means of simplifying our frequently complex electrical circuits. The voltage source (Thevenin circuit) and the current source (Norton circuit) serve as equivalents for one-port active networks and, as controlled sources, have already appeared as parts of the //-parameter two-port equivalent cir- cuit. The latter circuit will be employed to represent the transistor or tube in circuit analysis. With the proper values for the h parameters, we can represent the transistor as a circuit of resistances, capacitances, and generators and can write and solve circuit equations that demonstrate the amplifying effect of the transistor. REVIEW QUESTIONS 3.1 What is a "black box" intended to represent? 3.2 What do we need to know about the internal connections of a black box? 3.3 Why can we say that a voltage-source circuit is equivalent to a black box of one port? 3.4 What are the two measurements needed to determine the circuit elements of a voltage-source equivalent circuit? 3.5 How arc the circuit elements of a voltage-source circuit related to a current- source circuit ? 3.6 If the one-port box contains no energy source or is passive, draw the equivalent circuit. 3.7 Why are we interested in obtaining the maximum power output from some generators? Name two such sources. 3.8 What is meant by matching a load? 3.9 What is the output power efficiency of a generator with a matched load? 3.10 What kind of terminal loads are used in determination of the h parameters for a two-port equivalent circuit? 3.11 Why are the assumed currents directed inward at the ports of a two-port net- work? 3.12 Sometimes the use of a short circuit leads to generator damage. Can you sug- gest an alternative means of obtaining data to calculate the // parameters with- out using a short circuit? 3.13 Why are the h parameters called hybrid parameters? 3.14 What is the major property of a controlled source? 3.15 Why arc h, and h f called control parameters? 3.16 What is one advantage of rating amplifiers in decibels of gain? 3.17 What is the usual reference level when we state that an amplifier output is at 130 dB? 3.18 What is the meaning of a circuit input of -30 dBm? 3.19 Determine the logarithm of 0.00672. 3.20 Can you suggest why h, is negative to //, in the example in Sec. 3.6? 3.21 Why is the decibel well suited to measurements along telephone lines? 3.22 The noise level of a jet engine is measured at | 137 dB. What is the decibel noise level of 2 jet engines? Of 10 engines? PROBLEMS 3.1 In Fig. 3.9(a) we find V, - 107 V at open circuit; with a load of 200 £2 we find K, = 49 V. Determine the circuit elements for a voltage-source equivalent circuit. 3.2 Determine a current-source equivalent circuit for the circuit of Problem 3.1. 3.3 Under short circuit, Fig. 3.9(a) has an output current of 8.7 mA. With a load of 10,000 Q we find the port 1,1 voltage to be 57 V. Draw and label the circuit elements for a voltage-source equivalent circuit. 3.4 (a) What is the load that should be used for maximum power output with the circuit of Problem 3.3? (b) What is the maximum power output available from the 1,1 terminals? 62 Models for Circuits Active Network -Ol -oi ~L -ol ion -oi (a) (b) Figure 3.9 3.5 What load should be used at the 1,1 port to obtain maximum power output from the circuit in Fig. 3.9(b)? 3.6 Determine the element values for a current-source circuit equivalent to the circuit in Fig. 3.9(b). 3.7 By use of the basic definitions applied to the circuit in Fig. 3.10(a), calculate the h parameters. 3.8 Calculate the h parameters for the two-port circuit in Fig. 3.10(b). Draw the equivalent circuit. 3.9 A generator of I V is connected to 1,1 in Fig. 3.10(b). Draw an equivalent voltage-source circuit at the 2,2 port and label the circuit elements with their values. I o- 20 n -WA- 15 £2 -o2 lo- lon -WA/- -02 35 n: :sn I2fi lo- -o2 I o- (a) (b) -o2 Figure 3.10 3.10 Draw and label the circuit elements for a voltage-source equivalent circuit for the circuit in Fig. 3.11(a). 3.11 Transform the circuit in Fig. 3.11(a) into a current-source equivalent. Draw the circuit. 3.12 What is the matching load for the circuit in Fig. 3.1 1(a)? 3.13 Determine the voltage-source equivalent circuit for the circuit in Fig. 3.11(b) at the 1,1 port. What is the matching load? What is the maximum available power output to a load? 3.14 Determine the current-source equivalent circuit for Fig. 3.11(c). Draw the equivalent voltage-source circuit. Problems 63 ion ion |o VWV- + IOV-=- sn -VWv- lo- + 15 V-=- (b) 4n o VvVv 1 3 A (c) Figure 3.11 3.15 A microphone has an output at -56 dBm. It supplies an amplifier that is to have its output at + 37-dBm level. (a) What is the amplifier gain required in decibels? (b) What is the amplifier power output in watts? (c) What is the amplifier input in watts? 3.16 An amplifier takes 5 mW input power and has an output of 32 W. (a) What gain is present in the amplifier in decibels? (b) What is the dBm level of the output? (c) What is the dBm level of the input? 3.17 An amplifier of 34-dB gain is connected in cascade with an amplifier of 28-dB gain. If 1 /iW is the input to the first amplifier, what is the output power in watts from the second amplifier? 3.18 A radio receiver has an input resistance of 70 fi. The antenna supplies a cur- rent of 0.2 /iA to that input. The electrical power to the loudspeaker is 12 W. Find (a) The decibel gain of the receiver (b) The decibel level of the input signal, 1-mW zero level 3.19 A transistor is found to have h, = 28 CI, h, = 4 x 10~ 4 , h t - 0.98, and h = 0.6 X I0 -6 mho. In a circuit equivalent to that in Fig. 3.7(b), find V 1 if /, 1.5 //A. Him: Use the /i-parameter equations. 4 Junction Transistors as Amplifiers In 1948 Bardeen and Brattain found that the current through a forward- biased semiconductor junction could control the current to a reverse-biased contact mounted nearby. The result was the first solid-state control device and was called a transistor, as a contraction of the words transfer resistor. Such a transistor employs both holes and electrons in the conduction process and is said to be bipolar. Shockley later developed the field-effect transistor that employs only holes or electrons; it is therefore called a unipolar device. This will be discussed in Chapter 6. 4. 1 Transistor Voltage and Current Designations Agreement on abbreviations used for transistor voltages and currents is needed for accurate understanding of transistor circuits. We shall use lower- case letters to designate time-varying quantities and capital letters for dc quantities and for rms values of ac signal voltages and currents. Illustrated in Fig. 4. 1 are some of the variations to be expected; these include Quantity Example Toial current or vollage /' c , v B AC signal, rms value l c , V b DC value l c , V c Supply or bias V cc , V B b 64 The Junction Transistor 66 r\ I V / c / V / fa / , 3 / ' U J ha o 4 u — 73 \ / '"' u >c >c • Figure 4.1 Time Transistor current notation. The subscripts c or C, e or E, and b or B are used to identify the transistor internal elements; the collector, the emitter, and the base, respectively. 4.2 The Junction Transistor Junction transistors are three-layer sandwiches of n and p materials, as il- lustrated in Fig. 4.2. These transistors are made in two types, dependent on the arrangement of the materials us pnp or npn. Performance of the two types is similar. In one the majority carriers are holes and in the other they are electrons. The bias voltages arc also reversed in the two types. Junctions are present at the interfaces between the n and/) materials. The three layers are designated as emitter, base, and collector. The first junction between emitter and base is operated with forward bias. The second junction between base and collector is operated with reverse bias. For the pnp unit the base and collector are maintained negative to the emitter; while for the npn unit the base and collector are positive to the emitter, as shown in Fig. 4.2. The pnp unit will be used for discussion of transistor operation. The emit- ter material is heavily doped in comparison to the base and, with forward bias, holes move from the p emitter to the hole-poor n-base region. With a very thin base, in the range of a few thousandths of a millimeter, the holes arc attracted by the negative collector voltage. The reverse bias on the second junction makes that junction one of easy flow for holes from the n-base region and the holes are swept across the junction to the collector. Thus we have established a current of holes from the emitter to the collector. Positive holes are shown by the arrows as inward at the emitter and outward at the collector terminal. The base width is made very narrow compared to the average distance the free holes move before recombination occurs in an n material. Therefore, while a few holes meet electrons and rccombinc in the base, 90 per cent or 66 Junction Transistors as Amplifiers Emitter Base Collector Emitter Base Collector . .\ A, . /. Figure 4.2 (a) Junction transistor, pnp; (b) transistor, npn; (c) circuit symbols. more of the injected holes will travel across the base and reach the collector. A small flow of electrons will occur in the base lead, to resupply the negative charge lost to recombination in the base. This flow creates an outward base current, as shown by the arrow in Fig. 4.2(b). The hole current from the emitter to the base is varied by the forward voltage across the junction, in accordance with V in the diode equation of Section 1.11. Control of the emitter-base voltage by a signal voltage causes a signal variation in the hole flow to the base and a similar variation in the col- lector current. The transistor is a control element in which the emitter-base voltage controls the collector output current. The input power is low because of the low resistance of the forward- biased emitter-base junction, typically a few hundred ohms. The output cir- cuit carries the same current, however, but typically will deliver it to loads of thousands of ohms. It is thus possible to have power amplification with the transistor. The Volt-Ampere Curves of a Transistor 67 The circuit symbols in Fig. 4.2(c) show the forward direction of emitter- base current by the arrow on the emitter element; the direction of the arrow distinguishes between pnp and npn transistors. The npn transistor could be discussed in like manner by reversing the bias potentials to maintain forward- and reverse-biased junctions and by consider- ing the emitter current as composed of electrons. The arrows on the transistor of Fig. 4.2(b) indicate the directions of forward current. 4.3 The Reverse Saturation Current in Transistors The reverse-biased base-collector junction of the transistor is to be isolated by opening the emitter connection, as in Fig. 4.3. The main current of holes to the collector is removed but there still exists the usual saturation current of a reverse-biased junction, due to thermal pairs generated in the materials. Holes generated in the base material are swept to the collector by the negative voltage there and electrons generated in the collector are swept to the base. Figure 4.3 Condition for Icbo- The resultant current can be measured with the emitter circuit open as I CBO (meaning current, collector-to-base, emitter open). Current I CBO is always present with or without emitter current and is additive to the major i c com- ponent. Current I CBO is highly temperature sensitive and the operating tem- perature must be limited to keep I CBO small with respect to the desired control current component coming from the emitter. 4.4 The Volt-Ampere Curves of a Transistor The output curves, Fig. 4.4(b), are the fundamental means of explaining the control characteristics of a transistor. These are curves of actual currents and related voltages and permit us to predict transistor performance. They will 68 Junction Transistors as Amplifiers i c <mA) fa -.1 — ■ L 30 10 20 »CE (a) (b) Figure 4.4 (a) Transistor circuit; (b) output curves of a silicon transistor at 25°C (77°F). provide a basis for the circuit models that will simulate the action of the transistor in amplifier analysis. The slope of the curves for any i B value is given by A/ c Av CE and dimcnsionaliy this is the reciprocal of a resistance. Accordingly, we can measure the collector resistance of the transistor by the reciprocal of the slope as r c — Av c Mr (4.1) The low slope of the curves shows that r c is high ; it appears relatively constant for a given base current but becomes lower for increased values of base cur- rent. At values of collector-emitter voltage of 1 V or less the curves merge into the saturation line, at the left in Fig. 4.4(b). Control of current by the base is lost. The reciprocal of the slope is again a resistance, that of the collector- base junction as a diode. This minimum resistance of the collector-base junc- tion is known as R CE i,.t)- It is largely due to the material resistance in the collector region. The collector current is controlled by variation of the base current, which is, in turn, determined by the base-emitter voltage v Ht: . In the region bounded The Current Amplification Factors 69 by the saturation line, the line for i„ — 50 fiA., v c£ = 25 V, and the line for i B = 0, the characteristics are uniformly spaced and regular, the slopes are relatively constant, and this implies constancy of the various transistor param- eters. This bounded region will be the region of operation for this transistor in many types of amplifiers. Cutoff of the transistor occurs for i H = 0, which is also the line for / c = Iceo (current, collector-to-cmitter, base open). For silicon transistors this current is very small, typically 2 ft A, and the curve for /„ = will lie very close to the abscissa. For a germanium unit the typical I CEO value might be 100 to 200 ft A. 40 30 < 3 20 in 1 50°C \ 1 lo°c 1 / i 1 J 1 r-r^ / 0.2 0.4 0.6 0.8 1.0 1.4 Figure 4.5 Input characteristics for the silicon transistor of Fig. 4.4. The input curve of the transistor appears in Fig. 4.5. This shows the rela- tion between base current and base-emitter voltage in the forward-biased junction. This curve looks similar to a forward diode curve, which it is. There is considerable variation of v BK with temperature, as indicated. 4.5 The Current Amplification Factors In Fig. 4.2 we showed the currents that were physically present at the transis- tor terminals; they reversed when we changed from a pnp transistor to an npn transistor. To avoid continuing confusion and to allow us to calculate for a circuit and then use either type of transistor, we are going to define all three transistor currents arbitrarily as positive inward, as shown in Fig. 4.6. That is, i E + ic + 'a = (4.2) 70 Junction Transistors as Ampliliers Relations between the Amplification Factors 71 '£ -o "BE k (a) (b) Figure 4.6 Defined currcnis and voltages: (a) pnp transistor; (b) npn transistor. and obviously at least one current must be negative and reversed to satisfy KirchhofTs current law. We now can develop several useful transistor parameters. The relation between collector and emitter currents is a measure of the efficiency with which the charges are transported through the base. A change in emitter cur- rent will differ from the resultant collector current change by reason of the recombinations occurring in the base. We measure the efficiency of transport at constant collector-base voltage and state it as the ratio of a small change in collector current A/ c - to the small change in emitter current A/ £ . The param- eter is useful for small changes or small signals and is called the small-signal collector-emitter current amplification factor. This has a magnitude of Al£_L„ CO (4.3) Recombination current is kept small through use of a thin base layer and the value of a lies in the range of 0.90 to 0.99. A good approximation to a can be obtained by using the steady current values at a point on the output curves; that is, we can employ BS&-A ! « (4.4) as the static or tic collector-emitter current amplification factor. A second amplification factor relates a small change in collector current A/ c caused by a change in base current Ai B . This is determined at a con- stant collector-emitter voltage and is designated as the small-signal col- lector-base current amplification factor, written as h - A 'r] h " ~ ATj.. (4.5) Jpcfc'conitint Since i B is small by design, the factor /»,,'" ranges from 20 to 200. Again, we can approximate h f , by using the steady currents at a point on the output curves; that is, ki-kssk* (4.6) '// "Also called /? in some literature but that symbol will not be used here because of conflict with the notation used in feedback amplifiers. Equation 3.12, with i c as an output and i„ as an input value, will explain the choice of h f as a symbol for this amplification factor or current ratio. Example: Ati> cfi = 15 V and i B = 20 mA, the curve in Fig. 4.4 shows i c - 2.6 mA. Using Eq. 4.2, l E + i c + '* = i e + 2.6 + 0.02 = i t: - 2.62 mA Consequently, Eq. 4.4 shows for the approximate magnitude of a that H _ I 2.60 "-232 = 0.992 at point Q on the characteristics. Example: The constant value of v c -e requires that changes be made along a vertical line in Fig. 4.4. Using v CE = 15 V, and with changes from the point at Q, with i B = 20 //A down to i B = 10 //A, the corresponding change in i c is from 2.6 to 1.4 mA. Then, h (2-6- l.4)mA . 1.2 _ „ " ~ (0.02 - 0.0 1 ) m A _ 0.0 1 " If we use the dc value as an approximation, we have at the same point Q ''-^abTmA^ 130 ^^' 4.6 Relations between the Amplification Factors The algebraic sum of the currents is equal to zero by Eq. 4.2 and so A/* + A/ c + At, -- (4.7) Equation 4.3 was written for the magnitude of a but in Fig. 4.6 we can see that i E and l c are oppositely directed so that we write A/. . A A- (4.8) Inserting this definition in Eq. 4.7, _A^ a + A/ c - -M B A/ C (l -*)- — A/ fl A/ c a 1 -a (4.9) 72 Junction Transistors as Amplifiers The Load Line and O Point 73 We recognize the left side of the equation as the definition of h { , and so we may write ft/.- (4.10) (4.11) 1 -a Equation 4.10 may be rearranged to give 1 + A,. Both Eq. 4.10 and 4.1 1 will be very useful in later discussions. Another use- ful equation can be obtained from Eq. 4.10 by writing (1 - a)A„ = a Inserting Eq. 4. 1 1 and canceling h fl leads to 1 1 -a = 1 + A, (4.12) 4.7 The Load Line and Q Point A simple transistor amplifier appears in Fig. 4.7. Writing a voltage equation around the output loop gives V CB = Vcc ~ Rk (4.13) This is the equation of a straight line.The transistor output curve family also involves the variables v CE and i c ; by plotting Eq. 4.13 on the family of transis- tor curves, the dc load line obtained will locate all possible values of v CE and i c for the series circuit of transistor and load R at a given V^. Figure 4.7 A transistor amplifier. To draw the load line for Eq. 4.13 we use the axis intercepts. Insertion of i c = in Eq. 4. 1 3 gives an .r-axis intercept at x = V cc ; use of v CB = gives >-axis intercept my = V CC IR. In Fig. 4.8 a load line is drawn for V cc — 20 V, V CC IR = 40 mA, and R - 20/0.04 - 500 Q. Figure 4.8 Output curves of a silicon transistor at 25 C (77°F). The load line is the locus for all voltages and currents that can exist with the load and transistor in series. If alternating input signals are used as shown, a zero axis point or no-signal point Q must be chosen on the load line. The Q point is also called the quiescent point since the circuit is quiet or V, = 0. We rather arbitrarily choose a Q point and decide on the bias currents and volt- ages, the steady V CE , the steady collector current I c , and the base current I B . We use these biases to place the signal variations in a region of the curves where the transistor will operate in most linear fashion. The bias sources also supply the dc energy that the transistor converts to the ac signal. Circuits for establishing the bias currents and voltages will be discussed in Chapter 5. For true reproduction of the input sine current signal, the output ac wave must be derived from equal /„ excursions along the load line, each side of the Q point. As the signal voltage moves positive, the operating point moves along the load line up to A at the positive peak, back to Q, and down to B at the negative peak of the i B signal input. The output current i c varies correspondingly, as shown along the i c axis in Fig. 4.8. 74 Junction Transistors as Amplifiers Having selected a Q point, we can determine the h parameters of the transistor in the region around that point. Wc shall then use those parameters in the equivalent circuit of the transistor. The value of h fc can be found from a measurement along a vertical line in Fig. 4.8 at constant v CE . The change in i c per unit change in i B represents h f , and, for example, a change of /j from 200 to 150 ^A causes a change in i c from 16.2 to 1 1.7 mA. Then . _ (16.2 - 11.7)mA .. on " (0.20- 0.15) mA (0.20-0.15) The output short-circuit reciprocal resistance is defined as and this represents the slope of a constant i B curve in Fig. 4.8; it is apparent that h oc is constant over the central region. The input resistance is defined as h V, Av BK h "-T i --Ei7 This relation represents the reciprocal slope of the input curve in Fig. 4.5, as an example. The input signal variation about the Q point must be kept small for //,, to be considered constant. The requirement for constant values of the h parameters is the reason that h fr and the oiher h parameters arc defined as small-signal parameters. The parameter h„ can be found as the slope of a curve relating v CE and v Bt: for constant i c . 4.8 The Basic Transistor Amplifiers The transistor is an active amplifier element with three external leads, one connecting to the emitter, one to the base, and one to the collector. We shall use it in circuits as a two-port device with four terminals. As such, one of the transistor leads must be made common to the input and output ports. The choice is arbitrary and leads to the three connections in Fig. 4.9. These are the common-emitter (C-E) circuit, the common-base (C-B) circuit, and the com- mon-collector (C-C) circuit. These three circuits differ in performance and application. For example, we shall find that the C-E circuit is best for power gain. The C-B circuit is a load-matching device that permits a low-resistance source to be efficiently connected to a high-resistance output circuit and results in a voltage gain near unity. The C-C circuit reverses the resistance transformation property and gives a current gain near unity. Other differences in the characteristics of these three circuits will become apparent with further study. To indicate the common input-output electrode and the use of the C-E, Simplification of the Equivalent C-E Circuit C-E C-B C-C 75 tt-O 4/" \'< T " Vee 1 o — i- * o o 1- (a) (b) Figure 4.9 Defined currents in C-E, C-B, and C-C connections with (a) pnp transistors; (b) npn transistors. C-B, or C-C amplifier circuit, a second subscript is employed with the h parameters, as h f „ h lb , h oc . In this text we intend to use only the h parameters for the common-emitter configuration; however, conversion equations for all three configurations are presented in Sec. 4.14. 4.9 Simplification of the Equivalent C-E Circuit Any linear two-port circuit can be replaced with the //-parameter circuit of Chapter 3. We have just shown how the transistor can be connected as a two- port circuit element. Therefore, we can replace the C-E connected transistor in Fig. 4.10(a) with the /i-parameter circuit in Fig. 4. 10(b). The values of the/; parameters can be taken from the manufacturer's data or from the charac- teristic curves but greater accuracy will result if they are measured at the selected Q point. A simple common-emitter amplifier is drawn in Fig. 4.1 1(a), including the bias voltages V BB and V cc that establish the Q point. In Fig. 4.1 1(b) we have 76 Junction Transistors as Amplifiers h t B 'c V. 0* d'b ■ir I K, (a) Transistor (b) Figure 4.10 (a) The C-E transistor as a two-port clement; (b) the /i-parameter equivalent circuit as a two-port element. \h*>2 |o- B >' o2 lo- \ C h„y„\ "ff'h /~ Transistor (a) (b) Figure 4.11 (a) C-E transistor amplifier; (b) A-paramcter equivalent for (a). replaced the transistor with its equivalent circuit between B, C, and E. Since no ac signal voltage can appear across the dc bias sources, they are eliminated from the circuit. The output blocking capacitor is chosen so large that no ac signal voltage appears there and it too may be removed from the equivalent circuit. Later we shall consider its effects. With voltages V, and V„ as rms values, we now have the complete ac equivalent circuit shown in Fig. 4.1 1(b). The //-parameter circuit equations of Sec. 3.6 apply to this transistor amplifier between ports 1,1 and 2,2. Using voltage and current designations from Fig. 4. 1 1 we have V, = h„I b + h r .V (4.14) /, - h ft I„ + K,V (4.15) Because of the direction of I c and the assigned polarity of the voltage across the load, we must write *-- 5 (4.16) The Transconductance g„ Tl Using this relation in Eq. 4.15, we have — ^=h f .h + h M V. Solving for the input current 1„ and inserting the result in Eq. 4.14, we have an equation involving V, and V as variables. We can write the equation for the voltage gain as -1 A " ~ V, ~ />„(! +h„R) h„R -K, (4.17) The performance of the amplifier can be better understood if we can find a less complicated expression for the voltage gain. Fortunately it is possible to simplify the circuit and the resultant equations with small error. Generator h„V c is a control source that feeds back some of the output voltage to the input circuit. The effect is usually small and we are justified in assuming h„ — and in dropping the generator from the equivalent circuit. Values of 1/A„, approximate 100,000 SI and as such are negligible in effect when in parallel with load R values of 1000 to 10,000 CI. The product li„,R then ranges from 0.01 to 0.1 and h a ,R can be dropped in comparison to unity in the denominator of Eq. 4.17. By making h„ = and h at = 0, we obtain the simplified equivalent circuit for the C-E amplifier in Fig. 4. 12(a). The equation for the voltage gain is simplified from Eq. 4. 17 to " ~ V, ~ h„ The two assumptions made above may seem arbitrary; however, we should not expect close agreement between computed values and laboratory practice because of the considerable variation in the transistor parameters between units of the same type. Values given by the manufacturer are average parameter values. For example, while l\ f , may have an average value of 100, the actual values of this parameter may range from 50 to 200 in transistors of the same type. The simplified equivalent circuit is amply justified by the saving in work and in increased understanding of transistor circuit operation. (4.18) 4.10 The Transconductance g n Equation 4. 1 8 for the C-E amplifier voltage gain employs the ratio h f ,/h lr . Reference to the /i-parameter definitions shows us that (4.19) The quantity I c IV b , is the reciprocal of resistance or a conductance with units 78 Junction Transistors as Amplifiers The Common-Emitter Amplifier 79 in mhos. It represents the output current obtained per unit of input voltage. Because it relates a current in the output circuit to a voltage in the input circuit, the quantity is a transfer conductance, called a iransconductance and given the symbol g m , where and from this can obtain the voltage gain as om is r K »» "I, (4.20) With g m — 0.01 mho — 10,000 //mhos, Eq. 4.20 indicates that we should have an output current of 10 mA ac for each ac volt input. !u. i J c *J±. + + v, '',>: ■ c \ V > E !±+. B C Jl + + '•; h„i i 6 « 8m V bc I k, E (3) (b) Figure 4.12 (a) Simplified C-E equivalent circuit (b) same as (a) with i! m Y tr as the source. In the equivalent circuit in Fig. 4.12(a), we see that the generator current and the collector current are the same and T, - h f Jt Using Eq. 4.20, we have h„h - g m V>, (4-21) We use g m V b , as the value of the current source in a revised C-E equivalent circuit in Fig. 4.12(b). The two circuits of the figure are completely inter- changeable, with one having its current source controlled by input current and the other by the input voltage. 4.11 The Common-Emitter Amplifier We can now use the simplified g m model of the C-E amplifier in Fig. 4.12(b), to evaluate the performance of that amplifier circuit. Voltage Gain We first express the output voltage as V. = -I t R - -g m RV» A,. = jf = -g m R (4.22) Current Gain (4.23) The current in the load R is h "gmVu" h t>h by Eq. 4.21 and so Au — -j- = h f . This is the current gain of the transistor itself. Input Resistance By observation of the circuit, we have D 'I Y_bt L /ft 'ft for the resistance facing the input signal source. Output Resistance The resistance measured at the output 2,2 port is found by reducing the signal source to zero. With V, = V h , = 0, the collector current source is also zero, or open. From the 2,2 port we see an open circuit but in practice we know that !///„, is present there as a large resistance. Therefore (4.24) R " ^h~ "or (4.25) Power Gain The power gain of the circuit is defined as power gain = P.G. = M„/4„| (4.26) (4.27) This result is usually converted to decibels. The transconductance g m may be considered as a transistor figure of merit and its effect can be seen in the sev- eral gain expressions. 80 Junction Transistors as Amplifiers 4. 12 Performance of a C-E Amplifier In a C-E amplifier we shall employ a pnp transistor with the following parame- ters: h it = 900 Q h f , = 25 h„ = 2.1 x 10" ^ h ot = 16 x 10" 6 mho 3 (a) (b) Figure 4.13 (a) Common-emitter amplifier: (b) with the simplified /i-parametcr equivalent circuit. The load R will be chosen as 2000 £2. With the circuit in Fig. 4.13, we have *» = fc = 9^-°- 0278mho The terminal resistances are R„ = h„ = 900 Q R . = -l- = 62,500 n The gains can be calculated as A,. = -g m R = -0.0278 X 2000 = -55.5 A„ = h t . = 25 P.G. = 25 X 55.5= 1387 In decibels this becomes P.G. dB = 10 log 1387= 10 x 3.14 = 31.4 dB Had we used the exact expression for voltage gain, Eq. 4.17, we would have found the gain to be —53.8 compared with -55.5 above. The use of the approximate circuit and gain expression results in an error of only 3 per cent in the voltage gain. We can conclude that the C-E amplifier has moderate input and output resistances and good voltage and current gains. It is found to have the highest Conversion of the h Parameters 81 power gain of the three basic transistor amplifier circuits and is widely ap- plied for this reason. 4. 13 Relation between A, and A r We can rearrange the C-E gain expression as (4.28) 4.--fc»--fe*--4£ by reference to Eq. 4.20 and 4.23. Equation 4.28 is actually a general relation between voltage gain and current gain in amplifiers, which can be stated as . . load resistance ^ _ . R_ 1 input resistance 'R, (4.29) This result may often simplify the calculation of the several circuit gain figures. 4. 14 Conversion of the h Parameters The form of the /i-parameter equivalent circuit is the same for any two-port circuit, and therefore is the same for the C-E, C-B and C-C amplifiers. The parameter values, however, will vary with the choice of common element and Table 4.1 shows these relationships. Since the common-emitter parameters are most readily available, our circuit analyses will be carried out with those parameters. TABLE 4.1 C-B and C-C Parameters as Functions of C-E Parameters _ h„ *» - rrhj.-nj. n,b . hijlp, ll,, llf r I I h !• hie = hi, hoc = h , kf.- -(\+h„)s;-h f . h, c ~\ C-E and C-C Parameters as Functions of C-B Pa- rameters h,.= 1 - a h,c = — Sfl l^a /. . . 'i/j/iot — h,t& "" 1-a L _ llcb h, c ~\ 82 Junction Transistors bs Amplifiers 4.15 The Common-Base Transistor Amplifier For ihe common-base (C-B) amplifier in Fig. 4.14(a), the input signal V, is supplied between emitter and base. The input current is /, and is much larger than the input current for the C-E circuit. This implies that we have a lower resistance transistor input circuit. We use the dashed box shown in Fig. 4. 1 4(b) as the /;-parameter equivalent circuit for the transistor, with common- base h parameters. (O Figure 4.14 (a) Common-base amplifier; (b) the /i-parameler equivalent circuit; (c) equivalent g m circuit. Use of a conversion factor from Table 4. 1 allows us to write for the col- lector current From the C-B circuit in Fig. 4.14(b), we have V. b - h lb l. (4.30) The Common-Base Transistor Amplifier and using the conversion factor for h, b 83 We can determine the transconductance by taking the ratio of Eq. 4.30 to 4.31, to give us 'ft v ,b h„ I. (4.32) 1 + V The transconductance for the C-B circuit has the same magnitude as for the C-E circuit; the negative sign arises because we are using V, b for the input voltage instead of V bl . Using -g m and h lb = hj{\ + h ft ) we draw the g m model for the C-B amplifier shown in Fig. 4.14(c). The performance of the C-B circuit can then be calculated, using the common-emitter parameters. Voltage Gain We have from the circuit h = -g m y, b (4-33) Because of the polarity assigned to the output voltage, we write it as v. - -/«* - g m RV,> Since the input to the transistor is also the signal input, or V , b — V„ we have for the voltage gain A* - fy = g m R (4.34) Current Gain The load current is given by Eq. 4.33 and if we use Eq. 4.31 for V rb , we can write l c as / - &"> h <' l '°~ I M/,' The current gain can be obtained from this relation, as A _ h _ gJ'l. *» ~ % ~ • I hf. (4.35) We often find that h ft » 1 and the unity term in the denominator can be neglected, giving *,.= hftlhit = -1 (4.36) as a limiting value. 84 Input Resistance The input resistance at the 1,1 port is /? _ hit. Junction Transistors as Amplifiers V An rnr B ?-^ (Q) (4.37) This is a low resistance, as predicted. Output Resistance We make V, = and effectively this reduces the current source to zero or an open circuit. The output resistance measured at 2,2 appears infinite but in practice it represents l//i o6 = (I |- h fc )/h oe , which is usually over I MQ. Power Gain This is obtained From A„ b and A, b as P.G. -\A,. b A lb \-g m R (4.38) The current gain approximates unity, with 180° of phase shift. The voltage gain is equal to that of the C-E amplifier in magnitude. The major reason for using this circuit is to obtain maximum power transfer through impedance matching. This is accomplished by matching the low-resistance input circuit to a low-resistance signal source and the high-resistance output circuit to a high-resistance load. Since the current from input to output is essentially equal, the circuit behaves in a manner similar to a water pump, forcing water from a low-pressure system to a high-pressure system. 4. 16 Performance of the C-B Amplifier Using the same transistor as in the C-E amplifier example, we find the perfor- mance of the C-B circuit with a load of 2000 Q. h„ = 900 Q h„ 3 negligible h„ = 25 h„, = 16 x 10" 6 mho = negligible We calculate g m = /,„//,„ = ffo ^ 0.0278 mho. The voltage gain is A tb = g m R = 0.0278 X 2000 = 55.5 The current gain is A - *A. 0-0278 x 900 *'"- TFry, 26" = - 0.96 The Common-Co/lector Amplifier The power gain is P.G. = \A, b A lb \ = 55.5 x 0.96 = 53.4 P.G. dB - 10 log 53.4 = 10 x 1.73 = 17.3 dB The input resistance is R » ~ ""■ T+T7, ~ "26 ~ J " and the output resistance is 1 1 + h rt _ 26 _ , fi2 mq 85 h ol ~ 16 x 10- This is very large, as assumed. 4.77 The Common-Collector Amplifier The common-collector (C-C) amplifier in Fig. 4. 1 5(a) is also called an emit- ter follower. This name is justified when we write the voltage equation around the input loop in Fig. 4.15(a) as V, - V b , - V„ = (4.39) Making the input signal V bt small, we have V,= V (4.40) The output voltage is approximately equal to, or follows, the input voltage. The voltage gain is, of course, near unity. The transistor is in the normal B, C, E connection and between those terminals we simply substitute the g m model of the transistor, as in Fig. 4.15(b). The input resistance to the emitter is h„ and the current source is Km 'bf From the load circuit V. = (/* + hW (4-41) (a) (b) Figure 4.15 (a) Common-collecior amplifier; (b) g m equivalent circuit. 86 Junction Transistors as Amplifiers Performance of the C-C Amplifier 87 By definition in Sec. 4.10, we have I< = g«,V bt - h f ,l b (4.42) Using Eq. 4.42 in 4.41, we have K - (/» + h ft I b )R - (1 | h fc )RI b (4.43) Using Eq. 4.43 and V b , =- h,,l b in the input loop equation, Eq. 4.39, we have K <=[»,. + (1 I h rt )R)I h Input Resistance The input resistance at the 1,1 port of the amplifier is R le => V,\I b , which can be evaluated from the result above as •b Since h u > 1 is a usual condition, we then have R lc ^h„ + h,.R which is a large resistance, much greater than h lt . (4.44) (4.45) -o2 -R„ -o2 Figure 4.16 For the output resistance of the C-C amplifier. Output Resistance To obtain the output resistance at 2,2 we short-circuit the signal source V„ which reduces the control generator to zero or an open circuit. The circuit at the output port then becomes that shown in Fig. 4.16, with //„ in parallel with R, so ""--KTR «■*> which is a low resistance, less than h„. Current Gain The output current in the load of the C-C amplifier is /, and we know that /. - -(/ b + I.) from the KirchhofT current law. But I, = //,,/» from Eq. 4.42 and the current gain can be obtained as •b >b (4.47) Voltage Gain as The voltage gain can be derived by use of the principle of Sec. 4.13, written "re — "te p hr.R *■•(' ' e«) using A, c from Eq. 4.47 and R le from Eq. 4.45. The expression above then becomes ■ _ g m R A.- i i gji (4.48) which has a value less than but near unity. One use of the emitter follower is as a unity voltage gain amplifier to isolate one circuit from another; this might be the case if we supply a tele- phone line with the output of the amplifier. The C-C circuit is also widely used because of its high value of input resistance, which is much larger than can be obtained from a C-E amplifier. The C-C amplifier output also provides a match to a low-resistance load since R need be only 1000Q or so. This impedance transformation property, from a high input resistance to a low output resistance, is the inverse of the action of the C-B circuit. 4.18 Performance of the C-C Amplifier Using the same transistor employed for the C-E amplifier, and with R = 2000 Q, typical C-C performance can be calculated. The value of g m = 0.0278 mho, as before. h„ = 900 n h,. = 25 h„ ~ negligible /;„, = 16 X 10- 6 mho .*» = negligible The voltage gain is A - gn,R " 1 + gjt 0.0278 x 2000 1 + 55.5 = 0.984 and this approaches unity and has no phase shift. 88 Junction Transistors as Amplifiers The current gain is — h t , ■= —25, showing a 180° phase shift. The power gain is P.G. - | A VC A, C \ = 0.984 X 25 = 24.6 P.G. dB = 10 log 24.6 = 10 x 1.39 = 13.9 dB This is a low value of power gain. The input resistance is given by use of Eq. 4.44 as K = K + (1 | h f ,)R = 900 + 26 x 2000 = 52,900 £2 Using the approximate relation in Eq. 4.45, we have R lc £ h„ + hf.R = 50,900 £2 and the difference is not significant. The output resistance is h„R 900 x 2000 *«- = 621 n h le + R 2900 which is quite low, as predicted. This design would be well suited to operate from a high-resistance microphone into a telephone line. 4.19 Comparison of Amplifier Performance Table 4.2 is introduced to summarize the predicted performances of the three basic amplifiers and to allow comparison of their respective capabilities. TABLE 4.2 Comparison of Basic Transistor Amplifiers C-E C-B C-C Input resistance, R/ h„ h„ 1 + h„ Output resistance, R Current gain. A, I Voltage gain, A. gmR gmR Power gain ll/,gmR gmR Power gain as a ratio to that of the C-E amplifier 1 1 hi. + h ft R h„R hi. + R at l hf.gmR 1 +g m R I 1 +g„R Table 4.3 adds the data from the several examples, again for comparison purposes. The data show that the C-E circuit has nominal input and output Transistor Manufacturing Techniques 89 resistances and the highest power gain. For those reasons it is the most generally used amplifier circuit. The C-B circuit finds application as an imped- ance matcher from low to high values, while the C-C circuit isolates the input from the output and matches high to low impedances. TABLE 4.3 Typical Transistor Amplifier Performance Transistor : h lt = 90on h/. = 25 h„ = negligible h„ = 16 x 10-« mho Km = 0.0278 mho 2s negligible C-E C-B C-C Hi 900 n 35 a 52,900 n Ro 62,500 n 1.62 Mil 621 fi A, 25 -0.96 -25 A,. -55.5 55.5 0.984 P.G. 1387 55.5 24.6 P.G. dB 31.4 dB 17.3 dB 13.9 dB 4.20 Transistor Manufacturing Techniques The manufacture of transistors employs the same basic purification and crystal growth processes already described for diodes. Subsequent processing of the semiconductor material leads to grown junction transistors, alloyed junction transistors, and mesa and planar transistors. Grown junction transistors arc produced by crystal growth from a doped bath of molten semiconductor, as diagrammed in Fig. 4.17(a). Change of the predominant impurity from p to n and back to p is made at precise moments to yield layers of the desired conduction properties. Wafers are then cut from the crystal to include sections of the junction regions. Critical resistance requirements for the several regions are hard to meet and the method is not widely used. Alloyed junction transistors are made by fusing a pellet of the desired impurity element onto both sides of a base chip, as in Fig. 4.17 (b). With an n-silicon base,/? impurity pellets of indium will alloy with the silicon to form injunctions at the interfaces, as for the alloyed diode. Precise control of time and temperature of the fusion process yields transistors in which the critical base width can be very thin. The remainder of the impurity pellets serves as the emitter and collector contacts. The process of diffusion is widely used in the manufacture of mesa and planar transistors. A substrate wafer of desired resistivity is coated with a 90 Junction Transistors as Amplifiers Cryslal Pulling Machine 3? P melt (a) Epitaxial iy p Layer E B C Oxide Layer £ (c) (d) Figure 4.17 (a) Grown pnp transistor material ; (b) alloyed pnp junction transis- tor; (c) diffused mesa transistor; (d) planar transistor. layer of a doping element, by deposition from a gaseous atmosphere contain- ing silicon and the desired doping material. Exposure to high temperature for a limited time follows while the doping atoms migrate to the desired depth in the wafer. If an n-silicon wafer is used with boron as the diffusing impurity, the surface of the wafer will become/) material to the desired depth. A second diffusion with an n impurity changes some of the p material back to n for an emitter layer. The result is illustrated in Fig. 4.18. The depths of diffusion are a few thousandths of a millimeter. The diffusion process can be confined to very small areas by use of pho- tographically applied chemical surface masks. The surface of the silicon is coated with a very thin layer of silicon dioxide, followed by a layer of photo- resist lacquer. The mask is placed over the wafer in accurate register and identical areas for all the transistors are exposed to ultraviolet light. Where exposed to light the photoresist is chemically changed and made inactive. The unexposed areas are chemically etched away along with the underlying silicon dioxide, leaving openings to areas of the silicon wafer. The silicon of these Transistor Manufacturing Techniques 91 all - « H E C o I0'< L .-" I0'° p' 10* Collector Impurity Density 7..... c 0.002 0.004 0.006 Distance from Surface (mm) Figure 4.18 Diffusion process to form p base and n emitter. electrode areas is available for further impurity diffusion. The process is repeated with different masks, resulting in superimposed electrode areas. The masks are similar to negatives, produced as much-reduced photographs of large-scale drawings. The masked areas are very sm'all and hundreds of tran- sistors can be produced on one silicon wafer cut from a 2- or 3-cm diameter crystal. In the process of epitaxial growth (epi, upon; taxi, arrange), a doped crystal region is grown upon the wafer with the same atom arrangement and crystal structure. Growth usually occurs from a vapor containing silicon and a doping material at an elevated temperature. The impurity concentration can differ from that of the substrate, giving lower or higher resistivity in a thin layer. Use of a high-resistivity collector wafer raises the breakdown voltage but also increases the saturation resistance and the collector voltage drop at high current. By epitaxial growth, it is possible to place a high-resistivity but thin collector layer on a low-resistivity wafer, giving both high breakdown voltage due to the high-resistivity material at the junction and a low saturation resis- tance due to the bulk of the collector material. The use of an epitaxial layer is shown in the mesa transistor in Fig. 4.17(c). The mesa transistor may use an epitaxial layer on a p wafer, followed by an fl diffusion to form the base region. A second diffusion is applied to a small area through an unmasked opening in the silicon dioxide and a small p region formed for the emitter. Excess n material is then etched away to reduce the size and electrical capacitance of the collector-base junction. The name mesa is derived from the similarity of the completed transistor to the desert mesas of the western United States. The planar transistor in Fig. 4.17(d) is produced by diffusion of an n impurity to the desired depth in the p chip through openings in a silicon dioxide layer, masked as described above. The process is repeated and a p impurity is diffused to form the emitter region in the previously diffused base. 92 Junction Transistors as Amplifiers Silicon dioxide is added to reduce surface leakage and aluminum is evaporated through openings in the dioxide layer to form the necessary clement connec- tions. 4.27 Comments The junction transistor represents two back-to-back diodes, with the signal voltage controlling the current through the forward-biased input junction. This current is extracted through the reverse-biased output junction as a cur- rent source. In Chapter 3 we developed algebraic methods of active circuit analysis and a general //-parameter equivalent circuit model. This circuit, being equiva- lent to any active linear circuit, is used as an ac equivalent for the transistor by assignment of/; parameters measured at the ports of the actual transistor. The transistor becomes a set of circuit elements and a source, and for ac signal analysis we have no concern for holes, electrons, junctions, and biases. Since the output of a transistor is a varying current and we require a voltage for input to a cascaded transistor, we use a load resistor to provide conversion between output current and output voltage. There are three basic amplifier forms, the C-E, C-B, and C-C, for which we employ the same equivalent circuit model. This is the g m model for the active source, in which the internal current is made dependent on the input signal voltage. This g m model will be applied for the field-effect transistor and vacuum tube as well. REVIEW QUESTIONS 4.1 Draw the circuit symbol for a pup transistor; show and label the three assumed currents and the three voltages. 4.2 Repeat Question 4.1 for an npn transistor. 4.3 What is meant by I c , I B , V b „ I c , I b , V BB , I E , V cc 1 4.4 Explain the meaning of npn and pnp when applied to transistors. 4.5 What is the collector polarity with respect to the emitter in a pnp transistor? 4.6 What bias polarities should be applied to the base and collector of an npn transistor, with the emitter as reference? 4.7 What kind of charges transit the base in an npn transistor? 4.8 Why are the charges injected into the base able to reach the collector terminal in a properly biased transistor? 4.9 Why is the impurity concentration made much greater in the emitter than in the base? 4.10 Why does I CBO vary with temperature? 4.11 What should be the allowable maximum temperature of a silicon transistor to keep I CB o small? Review Questions 93 4.12 The transistor is sometimes said to be a current-operated device; use the diode law and explain that it is also a voltage-operated device. 4.13 What currents and voltages are related by the output characteristics of a tran- sistor with common emitter? 4.14 On the input curve of Fig. 4.5, choose a Q point and identify it. What should V BB be to obtain that Q point? What would I B then be? 4.15 What is the cause of / ca0 ? 4.16 For a C-E transistor, define h rE in words. 4.17 Define the current gain a in words. 4.18 What is the approximate relationship between h PE and h f , at usual operating temperatures? 4.19 Define the saturation resistance for a C-E transistor. 4.20 Explain how the h parameters arc determined from the characteristic curves. 4.21 Why can h FB never be greater than unity? 4.22 If a is given, how do you determine /i/ f ? - 4.23 If hfE = 60 and l c — 15 mA, what is the base current? What is the emitter current ? 4.24 What physical measurement of the transistor should be reduced to increase 4.25 State one reason for choice of a C-B amplifier. 4.26 State one reason for choice of a C-C amplifier. 4.27 What is the major advantage of the C-E amplifier over the other forms? 4.28 Define A m A,, and P.G. What does the negative sign on a voltage gain figure mean? 4.29 Why is the input resistance of a C-B amplifier so much smaller than that of a C-E amplifier? 4.30 Compare the input resistance of a C-C amplifier to that of a C-B amplifier. 4.31 Why is the C-C circuit called an emitter follower? 4.32 A C-B circuit is sometimes called a collector follower; explain. 4.33 What circuit element value should be changed to make A vc approach unity in a C-C circuit? 4.34 How should a transistor be chosen to accomplish the purpose of Question 4.33? 4.35 What assumption has been made to reduce the C-E amplifier voltage gain to -gmRI 4.36 Describe the fabrication of an alloy junction transistor. 4.37 What is meant by the epitaxy process? 4.38 What is a mesa transistor? 94 Junction Transistors as Amplifiers PROBLEMS 4.1 For ihe transistor in Fig. 4.8, find /« Tor a Q point at / c = 15 mA, with Vcc = 12 V and a load of 500 ft. 4.2 Find l B for the transistor in Fig. 4.8, with V cc = 30 V and R 1200 ft, V CB = 15 V. 4.3 For the transistor in Fig. 4.8, the dc load line is drawn between V cc = 20 V, l c = and / c - 30 mA, V CE = 0. (a) What value of R is being used in the circuit? (b) What is l c if the Q point is selected at l B - -- 100 /iAl 4.4 Determine h FE for V CE = 20 V, 1 B - 250 #A for the transistor in Fig. 4.8. At the same Q point, what is the value of a? 4.5 A silicon transistor has A; c m 1.80 mA for A/ £ = 1.89 mA. What change in /'« will produce an equivalent change in i c f 4.6 The transistor described by Fig. 4.4 and 4.5 is biased by V BB ■ 0.9 V at 0°C. Determine l c and V CE for R 6000 ft, V cc = 30 V. Hint: Find the Q point from Fig. 4.5. 4.7 A transistor in a C-B circuit has I„ 105 /;A, / c = 2.05 mA. Determine h FE ; also find 7 £ . 4.8 For the transistor of Problem 4.7, we note that when i a changes i 27 //A, fc changes +0.65 mA. Find a and lt ft . 4.9 The >/ parameters for a transistor are measured as /;„ - 800 ft g m = 0.035 mho h„ - negligible //„, = 9 X 10" 6 mho With R 5000 ft and neglecting li or , find A„ A,, R,, and the power gain in decibels in a C-E circuit. 4.10 Determine R lr , A„, and A u for a load of 1000 ft in a C-E circuit with a tran- sistor having /;„ = 1500fi A/, =40 /;„ = negligible h ot = 5 x 10 -6 mho What error is created in A,., by neglect of //„,? 4.11 Find the power gain in decibels when the transistor of Problem 4.10 is used in the C-B circuit with R = 5000 Q. 4.12 Repeat Problem 4.10 for the C-C circuit. Also find R oc . 4.13 With the transistor of Problem 4.9. determine A rb , A lb , R lb , and P.G. dB in the C-B circuit with R - 1500 £2. 4.14 In a C-C amplifier we use R - 1500 Q with a transistor having /i„ = 1800Q gm = 0.018 mho h, e = negligible h , = negligible Find A vc , A, c , R, e , R oc , and P.G. dB . If h Bt = 9 x 10 -6 mho, find the per cent error in neglecting it in computing A lc . Problems 95 4.15 A transistor having h, t = 65, h„ = 850 Q. h„ negligible, and /;_, neg- ligible delivers an output of 6 V across a 1500-£2 load resistance in a C-E amplifier. (a) What is the ac input current? (b) What input voltage is needed? 4.16 A transistor having h„ = 1200 ft, h f , = 32, h„, = negligible, and h„ = neg- ligible is used for Q { and Q 2 in the circuit in Fig. 4.19(a). Determine the current gain for these transistors in cascade with R = 2000 fi. Find the overall A r . Hint: The load of Q, is the input resistance of Q z . (a) (b) Figure 4.19 4.17 Wc have a signal source with an internal resistance of 150ft connected to a C-B amplifier. What value of input resistance should the transistor have for power matching? With an input signal of V,„ - 0.1 V, what value of# m should the transistor have to give an output of 12 V across a load of 2500 ft ? 4.18 A signal source of 100,000 ft internal resistance is to be power matched by the input circuit of a C-C amplifier. IT //„ - 800 ft and g m - 0.025 mho, what value of R should be used? What is the resulting /!,.? P.G. dB ? 4.19 Draw thcg m equivalent circuit for Fig. 4.19(b) when using a transistor having h„ = 1250 ft, h f , = 35, h„ = negligible, and /;„, - negligible. What output resistance will be measured at the 2,2 port? What is the voltage gain? Choice of the Quiescent Point 97 5 DC Bias for the Transistor Transistor amplifiers must be operated with steady bias voltages and currents to provide the desired operating conditions for the emitter-base and collector- base junctions. The bias sources also supply the circuit energy. The transistor converts only a part of the dc input energy to ac signal output; the remainder is dissipated as heat and must be removed. This ther- mal loss and the resultant temperature rise place a limit on transistor opera- tion. The maintenance of the steady currents and voltages through circuit design will be discussed in this chapter. Biasing circuits are added to the amplifiers of Chapter 4, hopefully without reducing amplifier performance. We find, however, that obtaining stability for the bias collector current often causes a loss in performance. 5. 1 Choice of the Quiescent Point On the output characteristics, the usable region for transistor operation is defined by the maximum ratings of the transistor. In Fig. 5.1 this usable region is bounded by the following: 1. The horizontal line at maximum allowable collector current. 2. The saturation line for the transistor near v CB = 0, where the base current loses control. 96 3. The cutoff line at i„ = near the abscissa. 4. The maximum allowable value of collector-emitter voltage to prevent avalanching in the reverse-biased junction. 5. The hyperbolic curve set by the maximum safe transistor power dis- sipation. The maximum dissipation curve results from the transistor power rating for maximum allowable temperature, and the curve is drawn for In Fig. 5.1 this maximum dissipation curve is drawn for P d -^ 200 mW. For large power output the Q point will be located close to but below this maximum rating curve. Figure S.I Choice of a Q point for a transistor; R = 3750 CI. For linear operation, the Q point should be placed near the central por- tion of the region where the curves are most linear and uniformly spaced. For small-signal linear operation, there is no unique location for the Q point but signal swings along the load line should remain within the linear region. Any Q point in a region having constant h„ h f , and lt values will give equal performance for a given load. 98 DC Bias tor the Transistor Variation ol the Q Point 99 'c /A\ h 1 \ fN i X / \ v* ,T\ *" \ xX YT" Y"—-. — x ^ "a (h) Figure 5.2 (a) Positive peak clipping; (b) negative peak clipping, A sine input signal applied to a Q point at A, Fig. 5.2(a), can cause output distortion at the positive peak, due to transistor saturation. A sine input signal applied at the Q point at B, Fig. 5.2(b), can drive the transistor into cutoff on the negative swing and distortion of output waveform results. At a central location at Q on the output characteristics, saturation or cutoff distortion is not likely to result for small-signal amplitudes. For this purpose we define a small signal as one whose amplitude is small when compared to the base-emitter bias voltage or current at the Q point. For V BE = 2 V, we might consider an input sine signal of +0.2-V peak, or less, to be a small signal. 5.2 Variation of the Q Point The current ratio h rE varies with temperature over a considerable range for a given transistor, as shown in Fig. 5.3(a). In addition, h FE is not closely controlled in manufacture and a typical rating might be h FE = 60 but with a range from 30 to 110. Since lc - h FE I B it can be seen that the Q point at l c ^ 4.6 mA, for I B = 80 fiA, could not be maintained for different transistors. For a fixed-bias current of 80 //A, the g-point current would range from 2.4 to 8.8 mA for various transistors of the same type. The latter value would lead to a saturation situation. In small-signal amplifiers there will usually be sufficient load resistance in the collector circuit to hold l c within safe limits. A change in h FE will cause a change in l c and l B , however. This may result in distortion through movement of the Q point toward cutoff on the input curve, Fig. 5.3(b). Cutoff distortion may also be created by further movement of the base- emitter bias point due to temperature changes. Fixed-base bias voltage, V BB = 0.84 V, will allow the base bias current to change from 40 to 240 //A as the temperature changes from to 50°C. The design of the base circuits should provide some stabilization of the g-point currents against changes in h FE and v BE due to manufacturing variations in transistors or to changes in temperature. The transistor reverse current J CBO is a sensitive temperature function, nearly doubling for each 10°C (18°F) rise in transistor temperature. In power amplifiers this can cause damaging increases in l c because of the small amount of resistance in the collector circuit. Methods of protection of the transistor against such damaging currents will be discussed in Chapter 12. To convert readily from one transistor current to another, we show their relationships in Table 5.1. TABLE 5.1 Transistor Current Relations From Ib lc To l B Multiply by I I *Te \ 1 I hn hFE 1 I'FE ~, I 1 hy E I + h fE ss h rE I + h, B ~ 1 hhE 1 100 220 200 1 80 1 60 jS I40 1 20 1 00 80 60 DC Bias lor the Transistor 20° 0° 20° 40° Temperature (°C) (a) 300 200 "fe/ 60° < 100 1 50°C II i ]0°c/ I 2 4 6 0. A i (b) Figure 5.3 (a) Variation of7/f £ for a silicon transistor; (b) variation of v BE with temperature. 5.3 Fixed Transistor Bias The circuit in Fig. 5.4(a) is perhaps the simplest form for base-current bias but it is the least satisfactory in compensation for changes in h FE . It can, however, effectively reduce bias current changes due to temperature varia- Fixed Transistor Bias 101 tion of V BE . Writing a voltage equation around the input loop of Fig. 5.4(b), we have Vcc - RbIb V be - and we solve for the base current as r _ ' cc • H V rr ~ V„ R„ But because V cc » V BE , we have J ~ 'cc Ib = ic b (5.2) (5.3) This shows that changes in V BE due to temperature have little effect on the bias current I B if V cc is large. The choice of R B then determines the bias current for the base. A -=r Vcc ^ (a) (b) Figure 5.4 Fixed-bias circuit analysis. (5.4) The following equation may be written for the output loop: V C c - Rlc -Vc* = But by definition of h FE 'C = "FE' B and so transposing and substituting in Eq. 5.4 we have Vce — V C c ~ R?c = V cc — h. . Rl With V cc and R fixed and l B a constant bias current, then Eq. 5.5 shows that a change in h FE must change V CE and this causes a shift in the Q point. It would be necessary to adjust the bias current by changing the value of R B in each amplifier completed in a production run. Readjustment of R B (5.5) 102 DC Bias for the Transistor would be necessary lo compensate for variations of h lE every time a new transistor were placed in the circuit. It should be obvious that a better bias circuit is needed, one that will prevent shifts of the original Q point for changes in h FE and V BE . 5.4 The Four-Resistor Bias Circuit The bias circuit in Fig. 5.5(a) uses four resistors and provides improved stability of the Q point. The input circuit resistors /?, and R x are used to give fixed bias, while the emitter resistor R E provides a bias voltage that varies with I c . This compensates somewhat for changes of h PE . Consider first the input circuit, which is redrawn in Fig. 5.5(b). We assume I B <S /, or that /, = I 2 . If I„ is in the microampere range and if /, and /, are adjusted to the fractional milliampere range, then our assumption is valid. A suitable selection is to make R t + R 2 = 60,000 to 100,000 fi. At the B, E terminals we can replace /?, and R 2 and the voltage V H with a voltage-source equivalent circuit. With R, and R 2 in series and l B negli- gible, the open-circuit voltage at B, E is given by the voltage-divider ratio V nr = V R = R* /?, + R 2 (5.6) If we short-circuit the B, E terminals, the short-circuit current becomes (5.7) Then, by our rules for deriving the voltage-source equivalent circuit, R' = Re = -7* = __M> (5.8) VcdRx ~ Rx + *2 This is the value for /?, and R 2 in parallel. The resultant voltage-source cir- cuit is drawn at the input in Fig. 5.5(c). Writing a voltage equation around the input as redrawn in Fig. 5.5(d), we have -V B + R B I B + V BE - R E I E - (5.9) We can replace I E with 1b - "(/* + Ic) - -(I I h FE )l B and have -V B + R B l B I V BE -i (1 + h FE )l B = Solving for the base current, we find /„ = V.-Vi BE V*-Y* Rb-tO +h FE )Rt I , _,_ (! +h FE )R E + ' Rb (5.10) The Four-Resistor Bias Circuit + 0^a (a) lo- 103 'l||K lo |f h \ -o + -=- y<x Rifv B -^. T (b) >'«,- + **iU (0 (d) Figure 5.5 (a) The four-resistor bias circuit; (b), (c), and (d) reduced circuits. For the fixed-bias circuit Ic-h FE l B (5.11) and for the four-resistor bias circuit, I c is h FE times the I B value in Eq. 5.10, leading to /r = y„-y» Rb , , (1 \-h FB )R B M Rb We can make I c less affected by temperature-induced changes of V BE by making V B larger. Since V BE approximates 0.5 V, we may make V„ — 3 V, 104 DC Bias for the Transistor as an example. We may also neglect unity with respect to h FE and then have l+h, <7T M } (5.12) With the fixed-bias circuit, I c was given by Eq. 5.11, and was directly affected by changes in h FE , with the bias current held constant. With Eq. 5.12 for the four-resistor circuit, however, we have h FE appearing both in the numerator and the denominator. It may be seen that the sensitivity of I c to changes in h FE can be reduced if we choose R E IR B correctly. If we make R E = 0, however, then Eq. 5.12 reduces to / — ^ B h 'c — Tr" Ft: Kb (5.13) and I c will vary directly as h FE , which is the undesirable situation in the fixed- bias circuit. In fact, making R E = in the circuit in Fig. 5.5(c) reduces it to the fixed-bias circuit. If we make R E /R B ~ 1, then the li FE (R E /R B ) term in the denominator would be the influencing factor. The h FE terms in numerator and denominator would approximately cancel and l c would be independent of h FE , which is a o © 1 4 9 / i pO.Oip i / — . % / y s / y * / / / 7 / / 0.03 0.05 m // Vs n 1 — / '^ U. 1 J 1.0 — 1 — 20 40 60 80 100 120 Figure 5.6 Curves for increases in l c due to change in li FE . Design of a Fixed- Bias Circuit 106 the result desired. R E must be small in magnitude or we lose signal gain and dc power, however, and R B must be large with respect to h„ of the transistor with which it is in parallel or we lose gain again. Thus some compromise between ideal bias stability and gain performance must be made. The sensitivity of J c to variations in li FE , for various values of R E /R B , is plotted in Fig. 5.6. Values of R E /R B in the range of 0.05 to 0. 1 usually lead to satisfactory gain and reasonable stability against changes in h FE . With the R E /R B ratio equal to 0.1, the value of I c will increase 70 per cent when h FE changes from 20 to 100. Without the compensation provided by R E , the value of I c would increase as shown by the curve for R E /R B = 0, or 500 per cent for the same h FE variation. Thus we have the design conditions for the four-resistor bias circuit: K fl = 3V 5^ = 0.05 to 0.I Kb We call R E /R B , or its equivalent in other circuits, the stabilizing ratio. This ratio serves as an index of stability, which increases as / c is made more stable by the circuit design. Figure 5.6 functions as a universal curve for predicting such stability as a function of the stabilizing ratio. 5.5 Design of a Fixed- Bias Circuit The fixed-bias circuit in Fig. 5.4(a) will be designed, using the transistor with characteristics of Fig. 5.7, with h FE - lOO. A Q point at V CE = 10 V, l c = 2 mA is chosen as a desirable location in the middle of the linear region of the curves. We usually assume that V cc = 2V CE and so we have V cc = 20 V. The load resistor can be found from the voltage equation around the output loop, Eq. 5.4; V cc ~ Rlc - Vce - R = cc Ic 20- 10 (5.14) "0.002" = 5000Q The remaining resistor is R B and the base current is Ic /„ = 0.002 100 = 20 x 10"«A = 20^A This value could also be read from the g-point location at V CE = 10 V, 106 DC Bias for the Transistor Design of a Bias-Stabilized C-E Amplifier 107 60 50 40 < a. 30 20 10 ' f2) — i — ' /! < £ 4 r .oad L JflJ 60 ^ r ix- inc 50 r£ — * v r \ 30 ' \ 20 rl \ s t 10 rl \ 0.5 "BE (a) 1.0 30 10 20 Has (b) Figure 5.7 Curves for the design example. I c = 2 mA in Fig. 5.7(b). Rewriting Eq. 5.2 we have p "cc ~ 'BE K B — J (5.15) For a base current of I B = 20 ftA at the Q point, we can go to the input curves of Fig. 5.7(a) and find that V BE at (I) must be 0.65 V. Then * H - 20 - 0.65 19.35 20 x 10* 20 x 10-« = 967,000 CI S 1 Mfi and our circuit design is completed. In the analysis of the circuit, an assumption was made that a large V cc would stabilize the circuit against changes of V BE with temperature. This can be shown by allowing V BE to be zero volts, in which case 20 * B - 20 10 " = 1 MQ Then we can make V BE = 1 V and find that R„ = 20- 1 20 X 10"* - 0.95 Mfi The required values of R B at 1 Mf2, 0.967 MQ, or 0.95 MQ all lie within the tolerance zone of a 1-Mf2, rhlO per cent resistor so that changes due to extreme values of V BE cause less circuit change than might be expected to occur in normal production runs from the tolerance on ^? a . With Ic = h fE I B (5.16) and l B fixed by our circuit design at 20 /xA, however, the collector current I c will vary directly with changes in h fE . Since the latter parameter is sensitive to temperature and to variation between transistors of the same type, the fixed-bias circuit gives no stabilization of the Q point with respect to fl, B changes. 5.6 Design of a Bias-Stabilized C-E Amplifier A bias-stabilized network for a C-E amplifier, using the transistor in Fig. 5.7, will be designed. This transistor has h„ = 650 SI and h tE = 100. Pre- viously it was pointed out that there is no unique location for the Q point for a linear amplifier since with a small signal and constant h fe , h„, and h ot values over a region of the transistor curves we would have equal amplifier performance at many Q points in the central linear region. Arbitrarily we select a Q point at I c £■ 3.2 mA along the I B = 30 fiA line. A supply voltage less than the rated K C£(n ,„, should be chosen. A value of 20 V was selected. The values for the four resistors, one being the load resistor, are to be determined for the circuit in Fig. 5.8(a). There are more circuit unknowns than there are relations to solve and so we must call on engineering experi- ence to determine some of the design values. + 20 9Vr, (a) (b) Figure 5.8 (a) Four-resistor C-E amplifier; (b) output circuit and currents. 108 DC Bias lor the Transistor Through the collector circuit, isolated at Fig. 5.8(b), we write a voltage equation Vcc - Me ~ Vce - RbVb i lc) =- Vcc - V CE - (R + R E )J C + Rah But since I a <C / c , we can then simplify the above to Vcc ~ Vce S (/? i *j)fc (5.17) We now have one equation and three unknowns, V CB , R, and R B . Experience indicates that the voltage across the transistor at the Q point ought to be about one-half of the supply voltage, expressed mathematically as Then Eq. 5.17 becomes v — ■ cc V -f = WR + R B ) (5.18) We have now reduced the unknowns to two. For our particular amplifier, with I c — 3.2 mA, we can write 10 - 0.0032(K I R E ) 10 R f R E - 0.0032 = 3100Q Since usual resistors are accurate to ± 10 per cent, we round off the numerical result. We can now draw the dc load line for R + R B on the transistor charac- teristics, from V cc = 20 V to i c = V cc j(R I R t ) = 6.5 mA, as intercepts. The Q point is placed at I„ = 30 fiA, V CE = 10 V as selected. The division of R + R E = 3100 Q. between collector and emitter circuits must now be determined. The emitter resistor was added to stabilize the steady collector current against variations in h FE . This purpose would dictate a large value for R E . The dc voltage across R E reduces the voltage across R, however, and the latter voltage limits the peak swing of the signal voltage across the load. Thus R E should not be large. As a rule, we make the emitter voltage V E about 10 to 20 per cent of the supply voltage and for this design we shall choose = 2V (5.19) We then have R E = L*^L* l E 2 0.0032 lc ^600fi (5.20) Design of a Bias- Stabilized C-E Amplifier 109 Consequently, /? = 3100- 600 = 2500 and the output circuit is complete. The base voltage V B is V B = V B + V BE (5.21) We go to the input curve, Fig. 5.7(a), and for a base current /„ — 30 //A, we find at (2) that V BE is 0.70 V. With V -~ R ^ (5 22) = 600 x 0.0032 = 1 .92 V s 2.0 V K ' Then, using Eq. 5.21, V„ - 2.0 -f 0.7 = 2.7 V We are able to write two design equations involving resistors R, and /J 2 : R,+Ri Rz ■ (5.23) (5.24) R:+R 2 ' cc We hope to make /, > 10/ a so that the current I B can be neglected in passing through /?,, as we assumed in the circuit analysis. Therefore, we choose /, S / 2 as 10 X 30 //A = 0.3 mA and from Eq. 5.23 we have «H Rz-^fz ' i = 3-3rTo^ 67 ' ooon From Eq. 5.24 we can find R 2 as V» (5.25) R, = (R, i /?,)- ' cc = 67,000^ _ 9000 Q (5.26) Then /?, = 67,000 - 9000 = 58,000 fi The design of the circuit is now complete and it is shown in Fig. 5.9. The bias resistor /? 2 is in parallel with h lt — 650 £2 of the transistor, and the shunting effect of/?, is negligible. That l c is stabilized can be determined. The value of R„ can be found from Eq. 5.8 as __RjRj_ R,+Rz 58 x 10 3 x 9 x W R B - 67 x 10 3 = 7800 110 DC Bias tor the Transistor The stabilizing ratio R E fR B is S. R. - 4^ - ^ - 600 R, 7800 Reference to Fig. 5.6 for h rE => 100 shows that the collector current can change only by a factor of 1/1.6 if h fE falls from 100 to 20. Thus our basic design choices are shown to be satisfactory, using the stabilization criterion of R t: IR„. r cc lb \lr lo lr- H( °- •c\ V. -o2 lo- Figure 5.9 Completed design for the four-resistor bias circuit. 5. 7 Voltage Feedback Bias The circuit in Fig. 5.10 uses an emitter resistor for stabilizing l c and adds further control through variation of 1„. If l c increases, the RI' C voltage drop increases, lowering the voltage at the collector. Resistor R f supplies base current from the collector and as I c increases, the base current falls. This change in I„ tends to oppose the original change in I c . Around the input loop, shown in heavy lines in Fig. 5.10, we have the voltage equation V cc - Rl' c - R,I B -V BE - R E l' c = (5.27) Since l„ is small compared to l c , we can neglect the branching of l B at point A at the collector and say £=/ c (5-28) Rearranging Eq. 5.27, V CC -V BE = (R I R E )I C +Rfh We can drop V BE as small compared to V cc . Then, using I B = I c lh rE , we can write the equation in terms of l c as rcc- (* + *, + jj£)lc Voltage Feedback Bias 111 + :ov Ol Figure 5.10 The voltage-feedback bias circuit. We can solve for I c and obtain /, Vcc- R F ^ R, Dividing out the R f term, we now have /r = R. 1 + h PE (R -: R E ) Rr (5.29) This expression for the collector current can be compared to Eq. 5.12 for the four-resistor bias circuit. We see that they are the same in form but differ in the stabilizing ratio, which now is /H Re S. R. - R, (5.30) The effect of this value of stabilizing ratio can be assessed by reference to Fig. 5.6. Since both R and R E are included in the numerator, the division of resistance between emitter and collector circuits has no effect on stability. Resistor R, can be determined from V CE = R,1 B + V BE 'CK 'BE ~ VCE h m Ib R t - (5.31) It is usually possible to make the stabilizing ratio and the stability for the four-resistor bias network larger than for the voltage-feedback circuit since R f is relatively large. The voltage-feedback circuit with R, saves one re- sistor, however, and avoids the power dissipation due to the current /, in the R„ R 2 network. This point may be significant in battery-operated equip- ment. 112 DC Bias for the Transistor 5.8 Design of a Voltage-Feedback Bias Circuit We shall use a transistor with the following values: / c = 2.3 raA, I B = 30 //A, V BB = 0.5 V, and h FB = 75 in a C-E circuit with V cc = 15 V. Making V CE = V cc \2 = 7.5 V, we find * + «—* 15 2 x 0.0023 2 3200 Q With R E l c = 0.I5K CC = 2.25 V, we can calculate that ff _2.25 2.25 £ : l c " 0.0023 and 7? = 3200 - 1000 - 2200 Q. Using Eq. 5.31, d 'ce ~ 'BE Rf ~ T m siooon 7.5 - 0. 5 30 x 10 i = 230,000 fi This completes the circuit design. The stabilizing ratio is S.R. = R + Rm 3200 = 0.014 ~ 230,000 From Fig. 5.6 we see that the l c value will change about 275 per cent for a 500 per cent change in lt FE . This figure for stability ratio is not so good as can be obtained for the four-resistor network, where we might have R„ s= 10,000 Q. Then bR - r- b Tom~ In the voltage-feedback circuit the value of R f is determined by base current and R f is large. The large R f value reduces S.R. as shown. 5.9 Bias for the Emitter Follower The bias circuit for the emitter follower, Fig. 5.11, will now be considered. We start with the four-resistor network but make R — 0. Resistor R E now becomes the total load resistance. Bias for the Emitter Follower 113 (a) (h) Figure S.I I (a) Bias for the emilter follower; (b) design example. Using K cc /2 as the voltage across the load R e , we have Vcc K- = W, + lc) Vcc 2I C and V E S RrIc = ~F The voltage V B at the base of the transistor must be V B - V„ + V R (5.32) (5.33) (5.34) The input resistance of the emitter follower is very large and l„ will be very small. Then /, £ I 2 and the voltage-divider ratio for R, and R 2 will accu- rately determine V B . Then V "- R x rR l Vcc (5.35) We have only this single relationship with two unknown resistors. Again we must rely on experience. A value of 60,000 Q may be arbitrarily chosen for R : + R 2 , after which we can solve for R, and /? 2 separately. We can use Eq. 5. 12 for determining l c since that equation was ob- tained for the four-resistor bias network that we are designing but with R = 0. That is, hrs I -^ i+h FE q? R (5.36) 114 DC Bias for the Transistor Review Questions 116 and the stabilizing ratio is SR =fc Due to the large value employed for R E in the emitter follower, the stability ratio usually exceeds O.l. This ensures excellent stability of / c in the emitter follower circuit. 5. 10 Design of the Emitter Follower Circuit Let us use a transistor with h FE — 100, V BE = 0.5 V, V cc = 20 V, and I c = 2.3 mA in an emitter follower (C-C) amplifier. We find R E from the g-point data. * £ - 2T 20 S 4300 CI , c 2 x 0.0023 It follows that V E = V cc /2 = 20/2 = 10 V and by Eq. 5.34 we find V B as V B = 0.5 -t 10 = 10.5 V We choose R, I R t = 60,000 Q and can find R 2 from Eq. 5.35 as R 2 = (R>+ RJ Vb (5.37) Then = 60,000-!^ = 31 ,500 ^ 30,000 Q. R, - 60,000 - 30,000 = 30,000 Q The circuit design is complete. With /?, = R t = 30,000 Q, the value of R B is - /?,/?, _ 3 X 10* X 3 X 10* » ~ R,+R 2 ~ 6 X I0« = 15,000 Q The stabilizing ratio is SR . _**= 430 ° R„ 15,000 = 0.287 Figure 5.6 shows that, with this large ratio, excellent stability of I c is provided against changes in h FB . The complete circuit appears in Fig. 5.1 1(b). 5.11 Comments We can now design complete amplifier circuits, including the necessary bias networks. These use only the source V cc , avoiding the cost of separate base and collector sources. Hopefully, these bias networks do not affect the gain or other performance figures of our amplifiers. The use of the emitter resis- tance R E often reduces the gain, however, and this must be allowed for in overall amplifier design. The use of the current-wasting resistors R, and R z introduces a cost in additional power. The effective value for /?, and R 2 , known as R B , shunts the input circuit of the transistor and wastes some of the input current, again reducing the gain. But the offsetting improvement in stability of the Q point and the elimination of individual amplifier adjust- ment in production are very significant. We have discovered that payment in some form is extracted elsewhere for every advantage gained in a circuit. Three basic bias circuits have been studied and the stability ratios are compared as S.R. Fixed bias Four-resistor bias Voltage feedback Iife (Eq. 5.I6) R B IR B (Eq. 5. 1 2) (* + **)/*/ (Eq. 5.30) Because of the flexibility in choice of R E and R B , the four-resistor bias net- work usually is the most stable form. REVIEW QUESTIONS 5.1 What is meant by the Q point? What factors do we consider in locating the Q point? 5.2 Give two reasons for h FE not being at the rated value. 5.3 Why docs the collector power dissipation bound the operating region of a transistor? 5.4 Why docs the maximum voltage bound the operating region of a transistor? 5.5 What is meant by the saturation line of a transistor? 5.6 What are the end points or intercepts of the dc load line? 5.7 How is the slope of the load line related to the resistance in the output circuit ? 5.8 Why must the Q point be located on the dc load line? 5.9 Explain how an ac signal or I b value shifts the operating point along the load line. 116 DC Bias for the Transistor 5.10 How docs / cflo vary with (cmpcrature? 5.11 Name one advantage and one disadvantage of the fixed-bias circuit. 5.12 What is meant by fixed bias? 5.13 What is the stabilizing ratio of the four-resistor bias circuit? 5.14 What range of I c variation could occur in a four-resistor bias circuit with S.R. = 0.05? 5.15 How does the fixed-bias circuit stabilize against temperature-caused changes in V„1 5.16 Name an advantage of the voltage-feedback bias circuit; name a disadvan- tage. 5.17 How is the emitter voltage usually related to V cc in an emitter follower? 5.18 What is the usual relation between V E and V cc in a C-E amplifier? 5.19 From the load line, explain why we choose V CE as one-half of Vcc to start our circuit design. 5.20 What is the stabilizing ratio for the voltage-feedback circuit? 5.21 Name three forms of payment we make to obtain stability of the Q point. PROBLEMS 5.1 For the transistor of Fig. 5.7, choose V cc = 20 V, / c - 4 mA, and V CB -- 9 V; draw the load line. What is the value of the load resistance? What is the base current 1„ at the Q point? # 5.2 For the transistor with characteristics in Fig. 5.1, choose a Q point for 1 B = 80 M and V CE = 12 V. (a) What / c is obtained? (b) With V cc = 25 V, what is the voltage across the load ? (c) What is the load resistance? 5.3 The Q point at C in Fig. 5.1 is used. With V cc ^ 40 V, what load resistance is needed ? 5.4 With the fixed-bias circuit in Fig. 5.4(a), find R and R B to place the Q point at C, Fig. 5.1, with V cc = 40 V. 5.5 A fixed-bias circuit is designed as in Fig. 5.12(a). (a) With V BE = 0.5 V, V CE = Vcc/2, determine the (?-Point values of l B and /c (b) What is h PE of the transistor at the Q point? 5.6 For the circuit in Fig. 5.12(b), (a) Determine R B to bring I c to 1.8 mA, ir/», E = 50. (b) What is the stability ratio for the circuit ? 5.7 The transistor of Fig. 5.1 is used in the circuit in Fig. 5.13(a), with V cc -= 25 V, V BE = 0.5 V, I c = 4.5 mA. Determine R, and R 2 values needed. What is the stabilizing ratio? What percentage will I c change if h VE changes from 40 to 100? 1 Problems 117 >+ 10 V <( ° o II- -|( ° i kn (a) (b) + 30 « ° Figure 5.12 «+25 (a) (b) Figure 5.13 5.8 With a Q point at l c = 3.5 mA, h, E = 60, Vcc = 25 V, and V BK = 0.5 V, determine the values of the other resistors needed for the circuit in Fig. 5.13(b). What is the stabilizing ratio for the circuit? 5.9 Determine the g-point currents and voltages for the circuit in Fig. 5.14(a), with V cc -\1 V, V BE = 0.6 V, and h fE = 55. 5.10 Determine the bias currents and transistor voltages for the circuit in Fig. 5.14(b), with V BE = 1-0.3 V and h PE = 75. Note: The circuit is an emitter follower. 5.11 Determine the design values of the resistances for the circuit in Fig. 5.15(a), with V cc = 20 V, I c - 6.7 mA, and h FE = 60, using the usual circuit assump- tions. Determine V CE and V E and the stabilizing ratio. 118 DC Bias for the Transistor Problems 119 ° It 250 k (a) + 20 V fb) Figure 5.14 (a) Figure 5.15 5.12 Lei R E = in Fig. 5.13(b) and calculate the bias currents and transistor volt- ages for R, - 150 kSl, R - 2.1 kSl, y cc = 9\, V BE = 0.6 V, and h FE = 40. 5.13 Using the fixed-bias circuit in Fig. 5.4(a), (a) Determine the collector-emitter bias voltage (V CE ) for R B = 250 kSl, R = 2 kQ, K cc = 12 V, V BE = 0.3 V, and h fE = 64. (b) Find l c and / fl . 5.14 For the circuit in Fig. 5.13(b), with R, - 250 k£2, rt - 2 k£2, R E = 500 kfi, Kx: = 9 V, V BE --= 0.5 V, and h FE = 55, (a) Find the dc currents and V CE . (b) What is the stabilization ratio for the circuit? 5.15 For the circuit in Fig. 5.13(b). find V CE for R, 47 kfi, R E =- 750 Q, R = 500 SI, V BE 0.5 V. h n = 55, and V cc = 18 V. 5.16 What value of emitter resistor would be needed to make the stabilization ratio equal 0.02 for the circuit in Fig. 5.13(b), with R = 750 SI. /?, = 50,000 ft. and h rS - 40? 5.17 Calculate the bias currents and transistor voltages for a four-resistor bias C-E amplifier with R, - 56,000 SI, R 2 = 5000 SI, R E = 750 Si, R - 6800 0. V cc - 24 V, V BE 0.6 V, and h, E = 50. 5.18 Design an amplifier circuit as in Fig. 5.13(b) for a transistor having h tE = 45, I c = 5 mA, V C c = 20 V, and V BE - 0.5 V. Make the usual circuit assump- tions. 5.19 For the emitter follower circuit in Fig. 5.15(b), find the value of Vg, for R B = 90 kfi, R E 1500 S\, V cc = 25 V, V BE = 0.35 V, and h rE -- 60. Also find the stabilizing factor and predict the I c change tf h Fl . changes to 100. 5.20 Design an emitter follower, using the circuit in Fig. 5.15(a) with R = 0. The transistor has li FE = 100, V BE - 0.5 V and V cc - 15 V, l c - 2.5 mA. Make the usual assumptions. 6 The Field-Effect Transistor The field-effect transistor (FET) was an early proposal by Shockley that had to wait for the development of new production methods to become a practical device. It is a unipolar device because the current is either of holes or of electrons, in contrast to the bipolar transistor of pnp or npn form. The cross section and consequently the resistance of the conducting path in this device may be controlled by a signal voltage applied to a gate electrode. With a high input resistance of 100 Mfi or more and generating less noise than a bipolar type, the FET is well suited as an input amplifier with low- level signals. 6. 1 The Junction Field-Effect Transistor Figure 6.1(a) illustrates the operating principle of a junction field-effe • tran- sistor (JFET). The thin slab of semiconductor has contacts at each <.. d, a source S for the mobile charges, and a drain D for extraction of the charges. A p electrode forms a junction on the /; wafer and is known as the gate G; the thin region under the gate is called the channel. If n material is chosen for the channel, the conduction is by electrons. Ifp material is used, the conduc- tion will be by holes. For discussion, we shall use n material for the channel. With a voltage 720 The Junction Field-Effect Transistor Depletion Region 121 Depletion Region Pincheil-OI'l Channel & H|lt (a) (b) Figure 6.1 (a) Low voltage applied to the FET; (b) in the pinch-ofT condition. V DS applied, electrons move in the channel from the source to the drain. There is a progressive voltage drop along the bar and, with the source and gate being connected, points in the channel will be positive to the source and gate. With a positive n channel and a negative p gate, the junction at the gate- channel interface is reverse-biased. As a result, a depletion region forms in the channel as show/i. This depletion region appears largely in the /; channel because the /?-gate material is more heavily doped. The voltage drop is distributed along the gate and the reverse voltage at the right end of the gate is larger than at the left end. Because of the greater reverse voltage, the depletion region at the right end of the gate is thickened, as shown. The depletion region has no mobile charges and the channel current is confined to the wedge-shaped portion of the channel. The drain current increases as V DS is raised, resulting in the curve of (1) in Fig. 6.2(a). As there is greater reverse voltage between gate and channel, the depletion region begins to pinch off the channel as in Fig. 6.1(b) and the rate of current increase falls off to (2) on the curve. With further increase in V os the pinched-off region lengthens and the current curve flattens to (3). This region of essentially constant current, relatively independent of V DS , is called the pinch-off region. Placing the gate at — I V to the source 5 further reverse-biases the junc- tion and drives the depletion region into the channel. Saturation of the current occurs at lower values of V DS and at lower currents. In the pinch-off region the current is sensitive to the gate-source voltage V os ; as such, we have characteristics suited to the use of the FET as a control device, shown in Fig. 6.2(b). The operation is said to be in the depletion mode, with the increased 122 The Field-Effect Trensistor (ii) (b) Figure 6.2 (a) Current variation with V D s, with gates connected to source; (b)an output curve family, showing l D controlled by V s- negative gate voltage depleting the channel of charges and lowering the channel current. The abrupt rise in current above (3) in Fig. 6.2(a) is due to an avalanche- type voltage breakdown in the depletion region between gale and drain and this places an upper limit on the gale-drain voltage. The breakdown voltage is designated BV DOO , the source being open-circuited. The input resistance is that of the gate-channel reverse-biased junction. The gate area is small so that the leakage resistance is of the order of 100 MQ. A depletion capacitance C us appears in parallel. This capacitance is that of the reverse-biased junction, due to the dielectric effect of the depletion region between the gate electrode and the channel. This capacitance may be in the range of 2 to 10 pF. Currents of milliampere size in the channel can be controlled by the gate voltage. With the input current from the gate extremely small, we obtain significant amplification in a circuit such as that in Fig. 6.3. Figure 6.3 The JFET in the common-source amplifier. The MOS Field-effect Transistor 123 6.2 The MOS Field-Effect Transistor The metal-oxide-semiconductor FET (MOSFET) has its gate electrode insu- lated from the channel by a very thin layer of silicon dioxide. A wafer of high- resistivity p silicon is used and n impurity is diffused into a region near the top surface to form an n channel of moderate resistivity. Low-resistance n contacts arc diffused through a mask at the channel ends as source and drain. The surface is covered with a thin layer of silicon dioxide and a small metal gate electrode deposited over the channel. The thickness of the insulating layer is usually less than 10" 3 mm. Application of a negative bias to the gate drives electrons from the n channel immediately under the gate, depleting the region of free charges. The thickness of the depletion region varies with gate bias and constricts the conduction area in the channel. In Fig. 6.4(a) the condition at pinch-off is shown. The drain current is large with zero gate voltage and is reduced as the gate is made more negative. This is the depletion mode of operation; a family of output characteristics is shown in Fig. 6.5(a). Metal Depleted n Channel p Region (b) Figure 6.4 (a) Depletion-mode MOSFET at pinch-off; (b)channel configuration of enhancement mode; (c) transfer curve for an n-channel enhancement-mode transistor. 124 < E < a The Field -Effect Transistor 10 ^— ^~~C= + 6 8 — -** +5 6 +4 ■1 +3 2 — + 2 - 1 — "; 12 16 20 (b) F/ffure d.5 (a) MOSFET output characteristics: depletion mode, n channel; (b) enhancement mode, p channel. When constructed with a p channel, a positive voltage on the gate repels holes from the wafer and a depletion region forms under the gate, as indi- cated in Fig. 6.4(b). There is no current in the channel. If the gate is made more positive than some threshold V T , however, the positive gate charge attracts electrons from the negative source and builds an // channel between source and drain. This is shown in black in the figure. Current now passes The Load Line for the FET 125 in this channel, with a transfer curve between voltage and current as shown in Fig. 6.4(c). The positive drain potential readily sweeps out electrons, the channel is narrowed at the drain end, and pinch-off occurs. With zero current at zero V s and an increasing drain current with increasing gate voltage, we have the enhancement mode of FET operation. The input resistance of the MOSFET is due to the silicon dioxide layer and can be as high as 10 9 to 10" Q. The gate has a length of about 15 X 10" 3 mm and the capacitance between gate and channel is about 1 to 4 pF. MOSFET construction is particularly adaptable to the processes of impu- rity diffusion and metal deposition that arc carried out in the production of integrated circuits. 6.3 Symbols for the FET In Fig. 6.6 we show the several circuit symbols used to identify field-effect transistors. In Fig. 6.6(a) and (b) the arrows show the materials used in a manner similar to the diode symbol; at (a) we have a p gate to an //channel and at (b) there is an n gate on a p channel. The arrows tell us the polarities of the needed bias voltages. The gate electrode identifies the source by being placed above 5. J$-o S v - — " D S v — ^ D S v -4--' D Wafer Wafer (a) (b) <c) (d) Figure 6.6 JFET: (a) n channel; (b) p channel. MOSFET: (c) //-channel deple- tion; (d) p-channel enhancement. The isolated gate symbol in Fig. 6.6(c) and (d) identifies the transistor as a MOSFET. The arrows in the wafer leads indicate the materials, again follow- ing the diode symbolism; at (c) we have an //-channel depletion mode and at (d) there is a //-channel enhancement-mode transistor. 6.4 The Load Line for the FET We may draw a dc load line on the characteristics of an //-channel JFET in Fig. 6.7, as done for the bipolar transistor in Sec. 4.7. The circuit in Fig. 6.7(b) is a common-source circuit. We write from the output circuit v DS - V DD - Ri D (6.1) 126 The Field-Effect Transistor 1 — 1 v« = (?_?N 1 Q ? _ 2 -v 3 -4 S £s 10 Yds (a) v ds v dd 15 20 lo 1(- |o- H( 02 '•R, r cc 'l)S (b) -02 Figure 6.7 (a) Depletion-mode, JFET characteristics; (b)common-sourcecircuit. which represents a straight line. This dc load line can be drawn for an .v-axis intercept at V DD and a j'-axis intercept at i D = V DD /R. These quantities should be so chosen that the load line traverses a region of uniform transistor characteristics. The Q point or zero V, point must lie on the load line for the circuit. A signal applied to the gate will vary v as and cause the operating point to move from Q up and down along the load line. If the output waveform is to be an undistorted image of the input wave, then the Q point must lie in a region of uniformly spaced output curves. The curve for v as — serves as one limit for the operating region. Point A at that limit should be in the saturation portion of the current curve. Voltage V DD should be less than the maximum rated drain-source voltage for the transistor. Obtaining Bias lor the FET 127 With these limitations, point Q of the figure seems a reasonable choice and a dc load line can be drawn through Q and V OD as an intercept. Wc can determine the value of load used as the reciprocal of the slope of the load line. The slope can be measured on the triangle formed by the load line and the axes as A/ V DD IR __ 1 V nn R slope = AVr (6.2) Wc then have R--= 12-0 0.0034 - 2= 3500 « We use the output characteristics to choose a Q point for bias determina- tion for the transistor. The (?-point location gives us the quantities I D , V as , and V DS . 6.5 Obtaining Bias for the FET The channel-resistance and the gate-control properties of FETs are subject to considerable variation among units of the same type. In addition there are changes due to temperature. Bias circuits must be designed so that some self-regulation of the Q-point drain current is obtained. The circuit should be able to compensate when one transistor is substituted for another of the same type but with differing parameters. The problem is illustrated in Fig. 6.8 where the drain-current versus gate- voltage transfer curves are plotted for three transistors of the same type. The zero bias-drain current I DSS varies from 25 mA for the high unit to 6 mA for the low unit. With fixed-voltage bias, V^ ■= —1.2 V, the drain current of the high unit would be 12 mA and that of the low unit would be zero, or the transistor would be in a cutoff condition. Fixed-gate bias is not a satisfactory solution to the problem. Self-bias, as shown in Fig. 6.9(a), is preferred over fixed bias. This elimi- nates one voltage source at the cost of two resistors. Resistor R, is large, usually 1 Mfl or more, and is present only to fix the average gate voltage at ground. This is accomplished since /„ = and there is no voltage drop in R,. The indicated polarities in Fig. 6.9(a) lead to an input circuit equation of y os + y* = o -V 0S =V S = R S 1„ (6.3) The negative sign shows that the gate is negative in relation to the source. If I„ increases, then V s rises and the gate is made more negative. But a more negative gate tends to reduce I D toward its initial value. Self-regulation of I D is thus accomplished by this circuit. The amount of stabilization of /„ 128 The Field-Effect Transistor 15 20 < S 15 10 l DSS - fl - VCG - 1 \ I /! si - / 1 / i / i / i ^ i o / /l / \ / i /\ ! -h 1 -3 -2 - 1 + 1 Figure 6.8 Drain current versus gate voltage for several 3NI28 FETs. is proportional to #„ however; large values of R s require increased V DD and also result in a reduction of gain. We may decide that about 15 per cent of V DD should appear across R s at 2-P°i nl current. Then the resistor voltage will be V S ~0A5V DD (6.4) Due to the flatness of the V os curve, we can read /„ and can find R s as Rs = ¥ (A) (6.5) The voltage drop across the transistor may be made equal to V DD \2 at the Q point and so we know that ft + J^S^p (fl) (6.6) Then we can determine the value of the load R. The load line for R + R s can be drawn from the x intercept at V DD to the y intercept at V DD I(R + R s ). The Q point and V DS are fixed by the intersection of the V os line and the dc load line. This completes the design of the self-bias circuit. The input and output capacitors are blocking capacitors, as before. Since they are expected to represent negligibly small reactances, they will not be considered at this time. The Four-Resistor Bias Network 129 10 < E KnO—H / ••«• = o v — L - 1 < - 2 r S \ Q 3 r I X N S," r N (a) 10 r DS (b) IS 20 Figure 6.9 (a) Self-bias FET amplifier; R + R, = 4300 fi; (b) characteristics and load line. 6.6 The Four-Resistor Bias Network The circuit in Fig. 6.10(a) requires one more resistor than the self-bias circuit but gives greater design flexibility in that the gate bias can be negative, zero, or positive as required. We choose a Q point in Fig. 6. 10(b) and find /„. Using the arbitrary rule of Eq. 6.6, R-\ R s = In (fl) (6.7) The voltage across R s may be arbitrarily chosen as 20 per cent of the total drop across R and R s so that r s i d ~ °^j»> = o.io y B (6.8) With R s determined, we can find the load R. In the circuit we show V os with gate positive to the source. If the gate is to be negative, then K c . v will carry a negative sign. Around the input loop V -V os -V s = Vo = Vos + V a (6.9) 130 The Field-Eflect Transistor "b.o_|(- 20 IS = e to { Vgs=0 -1 h Q - 2 !/ \ y \ 3 X -A -5 -4 i 10 20 30 40 (a) (b) Figure 6.10 (a) Four-resistor bias circuit ; (b) n-channel depletion FET, 3N 1 39. Since /„ = 0, we can use the voltage-divider relation to determine /?, and R 2 . That is, ^ = /?, + /? 2 ' DD (6.10) Again we have two unknowns with only one equation. We arbitrarily select R, + R 2 to draw a small current from V DD , compared to /„. Having R t ) R 2 assumed, we can solve Eq. 6.10 for R 2 and then obtain /?,. This completes the amplifier design. It may seem that much of this pro- cedure is arbitrary but we remember that transistor curve families are drawn for average units and differences between transistors will create circuit varia- tions that make more precise circuit design unnecessary. The self-regulating action of the circuit will usually bring the Q point to within about 10 per cent of the expected I D value for normal transistor and resistor variations. 6.7 Design Examples Example 1: Using the FET represented by the curves in Fig. 6.9(b) with a e-point current I D = 3 mA, with V DD - 20 V, find the exact Q-point location and the design values for R, R„ and R s for the self-bias circuit of Fig. 6.9(a). Selection of I D = 3 mA places our Q point somewhere along the V os ■= Design Examples 131 -3 V characteristic. But — V os = V s = 3 V and, using Eq. 6.5, we find ^ = ^ = D^3= 100 ° Q Then using (/? ■ R S )I D = K DD /2, we have from Eq. 6.6 R + R s = ^? 20 = 3300 Q 2(0.003) The load line of the figure is drawn between V DD — 20 V and a y intercept at i D = Y DD KR ->- R s ) = 6 mA. The Q point is at /„ = 3 mA, V os = -3 V, and V DS = 10 V. Arbitrarily we select R, = 1 MSI so the circuit resistances are r s = looo n R = 2300 fi R, - 1 Mfi Example 2: The circuit in Fig. 6.10(a) is supplied with a transistor having the characteristics in Fig. 6.10(b). Supply voltage is V DD = 20 V and the V os = —2 V line is considered a suitable location for the Q point of this /i-channci depletion FET. We shall choose (R -| R S )I D = ^dd/2 and this assumption fixes V DS = V DD /2 so that our Q point is located at V as = -2 V, V DS = ^ = 10 V. A dc load line for R ■ R s \s drawn from the .v intercept at V DD through the Q point. The Q point fixes I D = 6.5 mA. Then we have * + *, = !&.« 20 = i5oon 2/ D "0.013 We choose the voltage V s as 15 per cent of V DD or ^ = ^/ D = 0.15K oo 0.0065/^.-0.15 x 20 = 3V *^O565 = 470fi after rounding the resistance to the nearest standard value. Then we have R- 1500- 470 Q: 1000 Q We can design the voltage divider to give us the needed value of V c from V = V s + V as = 3.0 + (-2)= 1.0 V That is, the source is 3.0 V positive to ground and the gate is 1.0 V positive 132 The Field-Effect Transistor to ground. Thus the gate is -2 V to the source as we determined from the Q point. Since current through R, + R z results in a power loss, we choose R, + R 2 to take a current that is small with respect to I D . Selecting /, k 300 /zA, we have Rt+Rz = 20 _ 0.0003 ~ 0.0003 ~~ 67,000 n Because / = 0, the voltage-divider ratio will be accurate in setting V c and we have ^2 1/ Vn = R, +/? 2 V R^(R l+ R 2 )^3_ 'DO = 67,000^ = 3300 Q Then R, = 63,700 n. As the nearest standard resistance values, our circuit will employ r=\oooq /?, = 330on R s = 470 Q R z - 62,000 Q 6.8 The FET as an Amplifier As with the pnp or n/w bipolar transistors, the FET has three internal elec- trodes. We want to connect the FET, however, to four circuit terminals or two ports. Some FETs have four leads but one is a second gate that is largely used for bias control. Here our gate symbol indicates the ac signal or control element of the FET. The three choices of common lead provide three amplifying circuits, the common-source circuit, the common-gate circuit, and the common-drain circuit. The common-drain circuit is also known as a source follower and serves the same function as the emitter follower. In the common-gate circuit the high input resistance of the FET is lost. Depletion-mode operation is more commonly used for amplifiers, while the enhancement mode is used mainly for switching purposes in digital cir- cuits. 6.9 Circuit Characteristics of the FET The output curves for the FET predict the operation of the devices when used in an amplifier circuit. The JFET and MOSFET curves have the same general shape and as a result the devices may be discussed together. We choose the Circuit Characteristics of the FET 133 source as common and the voltages are measured to that electrode, as reference. As an amplifier, the FET is operated in the pinch-off condition where variations in drain current arc dependent almost entirely on gate voltage. The slope of the output curves is ^£- B -L (6.11) At; DS r d where r d is called the drain resistance of the FET. The low and nearly con- stant slope of the curves in the pinch-off region shows that r d is high and constant, almost independent of V os . This is a characteristic of a constant- current generator. The input resistance r os is considered very large and usually neglected. The effect of the shunting capacitance will be considered in a later chapter. A typical FET transfer curve, relating the drain current /„ to the input signal voltage v as , is drawn in Fig. 6. 11(a). This curve is found to be predicted by « D =/ D «(l-^) 2 (6-12) where f DSS is the value of /'„ with the gate shorted to the source S; this current is indicated by the small circle on the ordinate in Fig. 6.11(a). The constant V p is the pinch-off value of v DS , as at (2) of Fig. 6.2. It is found from a pro- jection of the slope of the transfer curve from / DSS , which intersects the abscissa at a voltage of V„/2. A useful transistor performance figure is the transconductance g m . This is the change in output current per volt change in input voltage. This is found from the slope of the transfer curve as ^- = ^r < mhos) (6.13) The slope is a variable and g m varies with i D . The extent of this change for a typical FET is plotted in Fig. 6.1 1(b). The selection of the 0-point current then determines the value of g m being used for a given FET and circuit. Equal changes in v as do not produce equal changes in /„ on the transfer curve because of the curve variation. If we reason that a curve is made up of short straight lines and if we choose a small segment of the curve, however, we can assume that segment is straight. Translated to the FET, this means that wc can use the FET for relatively distortionless amplification if we apply only small-signal voltages, causing i D to vary over only a small segment of the transfer curve; that is, we might restrict the input signal to ±0.2 V peak- to-pcak. Thus the FET is most often employed as a linear amplifier in the input, or small-signal, stages of a system. It is also useful in digital-switching circuits, where amplitude distortion is not important. 1 The Equivalent Circuit of the FET /i / / f / 1 f 1 1 r i 1— d- 1 'OSS i„ (mA) - S 3 V ± -2 2 (a) of 10,000 8000 6000 4000 2000 / / / 2 4 6 8 10 12 in (mA) <h) Figure 6.11 (a) FET transfer curve, depletion-mode FET; (b) variation of gm with i'd for a 3N128. 134 Typically, wc would expect r t to be in the range of 5000 to 50,000 SI for MOSFETs and above 100,000 fi for JFETs. The value of g m may be expected in the range of 1000 to 10,000 //mhos. This latter figure means 0.0I0 = A "«« and indicates that we shall have an output current of 10 mA ac for each ac volt input. 6. 70 The Equivalent Circuit of the FET Figure 6.12(a) shows the internal elements of an FET arranged as a two-port network in common-source connection. Too complicated to be readily analyzed, we reduce it to the simple equivalent circuit at Fig. 6. 12(b) by con- sideration of the relative magnitudes of the resistances and reactances. The equivalent circuit that is developed is satisfactory for applications not exceed- ing frequencies of a few megahertz. The element r„ is the reverse-biased junction resistance of the J FET or the silicon dioxide layer resistance of the MOSFET. These resistances are so high that we may consider r f , as representing an open circuit. The series circuit of C c and r c represents the capacitance between gale and channel and the series resistance of the channel. Being only a few picofarads and a few hundred ohms, their effect is negligible at low radio frequencies and they are eliminated from the equivalent circuit. Capacitance C, d is the gale-to-drain capacitance and includes the capaci- tance of the transistor mounting; being only 1 to 3 pF and of very high reactance we drop the element from present consideration. It was pointed out that the output current of an FET behaves as that of a current generator and so the internal generator is shown as the current source -o2 I °—\ — • Q*m V K> ,/d V » ©a-"* I -©2 |c~ -o2 r a\ I III -i AS _ -U2 / (a) (b) Figure 6.12 (a) The internal FET circuit; (b) equivalent circuit for the FET. 1 136 The Field-Effect Transistor Thus in Fig. 6.12(b) we have the same form of equivalent circuit as we previously used for the bipolar transistor; however, the input circuit of the FET takes zero current. The circuit elements are assumed constant around a given Q point and this restricts our operation with ac signals to a linear region of the output characteristics and to small input signals. Since the bias sources are not included, the circuit is useful for analysis with ac signals only. The effects of C c and r c and C, d at higher frequencies will be discussed later. 6.11 The Common-Source Amplifier In the common-source amplifier in Fig. 6.13(a), the input signal V, — V is applied between gate and source and the output V a is obtained between drain and source. In Fig. 6.13(b) we have replaced the FET between G,S, o2 lo— 1( 1 \Kc. S r e Vi 1 ■- Vac o (a) (b) Figure 6.13 (a) Common-source FET amplifier; (b) equivalent circuit for (a). and D with its equivalent circuit consisting of a current source and the inter- nal drain resistance r d . Resistor R is usually so large that it appears as an open circuit. Except for the zero input current, the FET common-source amplifier is similar to the C-E circuit for the bipolar transistor. Voltage Gain The parallel effect of r d and the load R is represented by R - r " R (6.14) The Common-Drain Circuit 137 The current g„V„ produces a voltage V across the output as 'o — 8m'^gt"f 8m r,R y,. • r d - r - R The negative sign results from defining the output voltage and current such that V„ = —Rl d - The negative sign indicates that a phase reversal has occurred between V„ and V B . The voltage gain in the circuit is obtained by dividing by V,„ leading to ' V„ g "r d \ R (6.15) Another useful form of this expression can be obtained by dividing numera- tor and denominator by r d , giving A.= ' + f (6.16) Usually R<g.r d and R/r d becomes small with respect to one and we then have A v ~-g m R (6.17) which is the same result as obtained for the C-E transistor amplifier. The voltage gain depends on the selection of a transistor with a high g„ and on the resistance chosen for R. Output Resistance The output resistance at the 2,2 port is defined as the resistance at that port with the input signal set to zero. With V, — V t , = the current of the current source is zero, a condition reached by opening the circuit of that source. The resistance remaining at the 2,2 terminals is r d and that becomes the output resistance of the amplifier. The value of r d is nominally high, perhaps 50,000 Q, and the gain approximates A v = —g m R- The circuit performance is similar to that of the C-E amplifier, except for the negligibly small input current taken by the FET. 6. 12 The Common-Drain Circuit For the FET common-drain circuit in Fig. 6.14(a), the input signal is applied between gale and the drain and the output is taken between source and drain. As noted previously, the circuit is known as a source follower. This is because the output voltage V„ is approximately equal lo and varies with the input V,. In this, the circuit performance parallels that of the emitter follower. We replace the FET with its equivalent circuit in Fig. 6.14(b). For better understanding, we fold down the upper half of the output circuit about the 138 The Field-Effect Transistor lo (a) (b) Figure 6.14 (a) Common-drain circuit; (b) and (c) equivalent circuits. line of the source and in (c) have resistors r d and R s in parallel; inspection of (b) shows this to be correct. The current source appears to have turned upside down but its outgoing terminal remains connected to S. Voltage Gain Using Eq. 6.14 for the parallel resistance of r d and R s , the output voltage is y. = g m R.v„ - g m *Vf*J y (6.18) 'r d + R s '" In this circuit the input signal is connected between gate and drain and from the circuit V, = V t , + V. V„=y,-K (6.19) The Common-Drain Circuit 139 (6.20) We make this substitution for V t , in Eq. 6. 18 and rearrange the terms so V (\ . 8™ r *R-i \ — o _JjRs_y °\ r d -, R s ) ~ gm r d ! R/> Multiplying by r d + R s and dividing by K„ the voltage gain from the input at 1,1 to the output voltage across R s is gm^Rs g„R s (6.21) A -&~ ' V, r t + R a + gjjl, l+ Rs +gmRs The drain resistance is usually large with respect ioR s and R s /r d will be small with respect to the unity term. The voltage gain is then approximated by This result would be less than but near unity since g m R s is usually larger than one. There is no phase shift between the input and output voltages in this amplifier. Equation 6.22 has the same form as obtained for the emitter follower. Since the equivalent circuit for the amplifier is the same, we should expect this result. Output Resistance As a demonstration of the method, we shall find the output resistance of the transistor at 2,2, with the load R s open, by use of the impedance rela- tion for a voltage-source equivalent circuit R' = /?„ = If. Written without R s , Eq. 6.20 gives for V„ K„ = (6.23) (6.24) 1 + g m r* With a short circuit across 2,2, we have V„ — and Eq. 6.19 gives V t , = V,. The current in the short circuit is l. c - g m V„ = g m V, (6.25) Dividing Eq. 6.24 by 6.25, we have R as g^y, ./ R , \+g m r/' _ r d (6.26) g m y, 1 + g m r d Usually g„r d » 1 and this equation reduces to a simple form, Sm (6.27) 140 The Field-Eltect Transistor Since g m is in the range of 0.00I to 0.01 mho, the output resistance of the circuit is small. Therefore the source follower, with only unity voltage gain, serves mainly as an impedance transformer, useful in amplification of a signal from a high- resistance input to a low-resistance output, such as a relay or a telephone line. The design of the bias circuit for a common-drain amplifier follows the procedure for the four-resistor circuit of Sec. 6.6 with R — 0. Example: Consider a source follower using a JFET with r d —- 50,000 Q and g„ = 0.0025 mho, as data given by the manufacturer of the JFET. Find the gain and output resistance with R s ^ 5000 £2. Using Eq. 6.2 1, we have g n Rs A.= 1+7* + *.*, 0.0025 X 5000 1 + sgno + 00025 x 500 ° 12.5 12.5 = 0.920 1 +0.1 If we had neglected the R s !r d term in the denominator, as in Eq. 6.22. we would have and the difference is negligible. The output resistance is r ~-L-_ !_ K °-g„~ 0.0025 = 400Q 6. 13 Design Example We shall perform the design calculation for a common-drain amplifier using the circuit in Fig. 6.10, with R = 0. The Q point is set at I D — 6.5 mA with y DU = 20 V, as in that figure. Using the arbitrary rule of Eq. 6.7, Rsln = and so D * DP 20 0.013 ^ 1500 Q Design Example The voltage V s is 141 V s = R S I D - 1500 x 0.0065 - 9.75 V This value is not quite the specified value of 10 V because of the rounding of the R s value. At the Q point, FW - -2 V and so Vo - Vos + Vs = (-2) + 9.75 = 7.75 V positive to ground. Since the gate current is zero, then resistors R, and R 2 serve only as a voltage divider for the gate voltage and we can arbitrarily choose /?, + R 2 = I Mfi. Then Eq. 6.10 gives R 2 = (/?, + /? 2 )ik = 10 s X 2^ = 387,500 Q = 0.39MQ Then R, = I0« - 0.39 X 10* = 0.62 MQ again choosing a standard resistor value. The circuit is complete with R s ^ 1500 n R t =-- 0.62 MQ R 2 - 0.39 MQ The value of g m at the Q point can be determined graphically by measuring Ai' . v as 1 V, from the 1-V curve to the — 2-V curve, and reading the resul- tant A/' D along the vertical line for v DS — 10 V, through the Q point. The value of A/„ is read as 3.5 mA and we have *, _ A/„ _ 0-0035 _ 0.0035 mho Aw os 1 The value of r d is large, as can be seen from the flatness of the v os = — 2 V curve at the Q point and we can calculate the voltage gain from Eq. 6.22: g m R s 0.0035 X 1500 t-*.** 1 + (0.0035 x 1500) 5.25 A v = 1 + 5.25 = 0.84 The output resistance is R.^ = 1 *„~ 0.0035 = 286Q 142 The Field-EI/ecl Transistor 6. 14 Using the FET as a Variable Resistance When operated near point (I) of the curve in Fig. 6.2, the drain-source chan- nel of an FET can be used as a voltage-variable resistance (VVR). The device represents a resistance of several thousand ohms, as shown in Fig. 6. 15. Currents will be of microampere order and voltages will be a few hundred millivolts. The device has some application in signal level control and expansion. The basic elements of a volume control application appear in Fig. 6.15(a), o It- -v. GST <6 G — o IS 000 / / i 0.000 %nnn — | — (a) 4 Vgs (b) -6 -8 Figure 6.15 (a) The FET as a voltage-variable resistance ; (b) resistance variation obtained. where the voltage across R is the output, as a varying fraction of V,. The gate voltage is varied by a rectified voltage derived from the input signal; as this increases, the FET resistance increases, passing on less of the input signal through the voltage-divider action of the circuit. The output signal is then controlled to a more constant level. 6.15 Summary The unipolar FET, with either n- or ^-conduction properties, controls the output current magnitude by means of a voltage applied to a gate electrode. Its most important feature is the very high value of input resistance. It is well adapted to production by methods of diffusion and metal deposition. Because of the zero input current, the design of its bias circuits is simpler Problems 143 than for the bipolar transistor but the methods of circuit design are the same. We also find the FET useful in the common-source and source follower cir- cuits, which parallel the C-E and emitter follower circuits in performance and applicability. Because of its curved transfer curve, the FET can give linear amplifica- tion only with small signals. This makes it most adaptable to input circuits. REVIEW QUESTIONS 6.1 Why is the FET called a unipolar transistor? 6.2 Describe how pinch-off is obtained in an //-channel JFET. 6.3 What is the construction difference between a JFET and a MOSFET? 6.4 Explain how a depletion-mode MOSFET operates. 6.5 What is meant by "enhancement mode"? 6.6 What is meant by "depletion mode"? 6.7 What is the significance of the arrow on the gate of a JFET symbol? Of the arrow on the MOSFET symbol ? 6.8 What range of resistances can we expect in the gate-to-channel path of a MOSFET? 6.9 What is the reason for limiting V uo for an FET? 6.10 Why do we limit FET operation to small signals? 6.11 The transistor in Fig. 6.7(a) has K oulm ,„ = 20 V. Bound the region for accept- able Q-point location for a linear amplifier. 6.12 Relate r d and g m to the characteristic curves of an FET. 6.13 Why is self-regulation of the drain current important in the common-source circuit? 6.14 Compare the voltage gain and output and input resistances of the common- source and common-drain circuits. 6.15 The common-source circuit is the counterpart of what bipolar transistor cir- cuit? Why? 6.16 The common-drain circuit is the counterpart of what bipolar transistor circuit ? Why? 6.17 An FET has# m = 6000 /zmhos at the Q point. In the common-drain circuit, what output resistance will be obtained ? PROBLEMS 6.1 For the curves of Fig. 6.5(a), with V uu = 20 V, R = 4000 fi, and V os = -1.5 V, find the Q-point current /„. 6.2 Determine R s if the circuit of Problem 6.1 is to be self-biased. 144 The Field-Effect Transistor 6.3 Design a self-bias circuit for a common-source amplifier using Ihe transistor in Fig. 6.9(b), with V DS = 12 V, I D = 3 mA at the Q point, and V DD 20 V. Determine R and /?.?. 6.4 An FET, Fig. 6.9(b), is in a common-source circuit with Q point at V DS = 7.5 V, I D = 4.0 mA, and V DD = 15 V. Find fl s , 7?, V os , /?,, and /{ 2 for R, + /? 2 = 1.25 MQ. 6.5 The 3N158 FET, with characteristics given in Fig. 6.7(a), is used in a common- source circuit with V DS = 10 V, /„ = 1.4 mA at the Q point. What should be the values of R, V D t» and V co for a good circuit design? 6.6 Design a four-resistor bias circuit as in Fig. 6.10, using V DD = 30 V, V os = —2 V. Select I D and suitable values for the four circuit resistors. 6.7 A depletion-mode FET has I DSS = 3 mA, V t = -4.25 V; find /„ for V os = —2.5 V by the square-law relation of Eq. 6.12. 6.8 A depletion-mode FET obeys the square-law relation of Eq. 6. 1 2 with l DSS = 8.4 mA, V, = -3.0 V. Find I D at V os = - 1-0, -2.0, -3.0, and V and plot the transfer curve. 6.9 Find g m at each V os value listed in Problem 6.8 by assuming A V os changes of 0.2 V and computing the resultant A/„. Plot a curve of g m versus /„. 6.10 What R should be specified for the circuit in Fig. 6.13(a) to obtain A v = -40 with g„ - 6000 fimhos and r d = 40,000 Q? What is the output resistance? 6.11 Given V DD = 30 V, /? 2 = 0.1 MQ, and /?, = 2 MQ for the transistor in Fig. 6.10, find R s to place Q at I D = 5 mA, V DS = 15 V, and V os = -2 V. 6.12 Determine/? for a JFET self-biased amplifier circuit as in Fig. 6.7(b), for a volt- age gain of 25, with r d ^ 40 kSl, g m 0.005 mho. Also, select a suitable value for R . 6.13 Find R, R s , and R t for the circuit in Fig. 6.9(a), with a Q point for the transis- tor at I D = 4.0 mA, V DS = 7.5 V. 6.14 An FET with r d = 50 kfi, R s = 2 kfi, and g„ 2500 //mhos is used in a common-drain circuit. What is the voltage gain? What is the output resistance? 6.15 Calculate the ac voltage gain of a common-source FET amplifier in the circuit in Fig. 6.7(b), with g m = 0.0045 mho, r d - 50 kQ, and R = 20 kQ. 6.16 What value of transistor # m is needed in the circuit in Fig. 6.7(b) to provide a signal gain of -40 if r d = 60,000 Q and R is chosen as 20,000 Q and R is I MQ? 6.17 A signal V, - 2 mV is applied to the FET amplifier in Fig. 6.7(b) with g m = 2500 //mhos, r d --= 40 k£i, R - 10 kfl, and R - 1 MQ. Find the ac output voltage V u . 6.18 What value of load resistor R s would match the output of a common-drain amplifier with g m = 0.0025 mho, r d = 40,000 Q ? Find the voltage gain with that resistor. 7 The Vacuum Tube The triode, or three-element form of vacuum tube, was the first electronic control device. It employs a heated electron-emitting cathode, a control grid of wire mesh, and an electron-collecting plate or anode, assembled in an evacuated glass, metal, or ceramic envelope. Additional grids are added to improve the electrostatic shielding between grid and anode, leading to the five-element pentode. Because of the need for heating power to induce emission of electrons, the large size and fragility, and the limited life, the vacuum tube has been superseded by the transistor at frequencies below 500 MHz and power levels below 200-W output. Many millions of tubes remain in service, however, so we give a brief discussion of tube and circuit theory here. 7. 1 Circuit Notation for the Vacuum Tube As for the transistor, there is an established system of nomenclature for circuit variables employed with vacuum tubes. The symbols lack the for- mality of those for the transistor, however. Again, we use lowercase letters to designate instantaneous values of varying currents or voltages and capital letters to denote rms or dc values. 145 146 The Vacuum Tube Subscripts b and p indicate anode circuit quantities and c and g indicate grid circuit variables. For example, i h = instantaneous anode current I h = quiescent value of anode current I p = rms value of the signal component of anode current v c = instantaneous grid-cathode voltage, also v, k V cc — grid circuit bias voltage V BB — anode circuit supply voltage Some tubes have more than one grid and numerical subscripts are used, with the grid nearest the cathode as number l. 7.2 The Triode The drawing in Fig. 7.1(a) shows the construction of the internal elements of triodes used at audio and low radio frequencies. There is a cylindrical nickel anode A, a helical grid G, and a central electron-emitting cathode K. The tube in Fig. 7.1(b) is designed for high-power transmitting service with air cooling and that in Fig. 7.1(c) is for high-frequency radio reception and illustrates a planar form of cathode and grid. If the free electrons within a metal are given sufficient energy, they are able to overcome the surface binding forces and can be emitted into space. The releasing energy can be supplied by heat in thermionic emission, by Glass Envelope Anode 5 cm I cm Ceramic (a) (b) Figure 7.1 (a) Low-frequency triode structure; (b) Eimac 8874 triode, 1000-W peak output up to 500 MHz; (c) small ceramic triode, usable to 450 MHz. The Triode 147 radiant energy in photoelectric emission, or by bombardment by atomic particles in secondary emission, or the electrons can be pulled out of the surface by the attractive force of a strong electric field, as in cold-cathode emission. For thermionic emission, the emitting cathode is most often a small nickel cylinder coated with a layer of barium or strontium oxides and heated to about 600 to 800°C (1000 to 1400°F). A low voltage is applied to a heater wire of tungsten to raise the nickel cylinder to emitting temperature. Such a cathode is said to be indirectly heated. Some tungsten wire filaments, impregnated with thorium, are used and operated at temperatures of 1600 to 1700X (3000°F). Wire filaments are heated by a current through the wire and are said to be directly heated. The electrons from the heated cathode reach the anode only when the (b) +. lo U- \o- -o2 -oi (C) lo- ta) -o2 lo- -o2 (d) Figure 7.2 (a) Triode circuit symbol and bias sources; (b) common-cathode circuit; (c) cathode follower circuit; (d) grounded-grid circuit. 148 The Vacuum Tuba anode is positive to the cathode and the triode conducts in only one direction. In transit the electrons pass through the openings in the wire grid. If the grid is negative to the cathode, electrons are repelled and the anode current is reduced. If the grid is made less negative, the anode current increases. It is seen that the negative potential between grid and cathode controls the electron flow and consequently the current through the tube. Practically no electrons can reach the negative grid and hence there is no grid current. As a result the triode has an infinite input resistance at fre- quencies through the audio range. Effects of the capacitances between the tube elements become important at frequencies of a megahertz or more and will be considered in Chapter 8. The circuit symbol for a triode and the applied bias potentials are shown in Fig. 7.2. Again we have three internal electrodes and wish to connect them to four terminals or two output ports. As a result of the choice of common electrode, we have three basic circuits. These are usually designated as the common-cathode circuit, the common-anode circuit or cathode follower, and the grounded-grid circuit with the grid common. All are diagrammed in Fig. 7.2. Our conventional current is again defined as positive inward and shown as i p from anode to cathode in the figure. 7.3 Triode Character/sties The output curve family for a typical triode is drawn in Fig. 7.3(a). The region of linear, equally spaced curves is bounded by V c — and by the maximum rated anode loss or dissipation to maintain a safe operating temperature. The loss limit is determined by P*=VJ b (W) (7.1) and a limiting hyperbola is drawn for P d — 0.6 W in the figure. Opposite changes of anode voltage and grid voltage are offsetting in effect on the anode current. The anode current is more sensitive to the grid voltage since the grid is closer to the cathode than is the anode. We measure -this sensitivity by the amplification factor n, defined as the ratio of anode voltage change to grid voltage change needed to keep i b constant. That is, (7.2) Triode Characteristics 149 - 2 i b (mA) The negative sign arises because the anode voltage and the grid voltage must change in opposite directions to maintain constant current. Values of n for triodes range from 3 to over 100. - 12 (b) Figure 7.3 (a) Output curve family; (b) transfer curve family. The reciprocal of the slope triangle of Fig. 7.3(a) defines the plate resis- (7.3) lance r p as r =^1 160 The Vacuum Tube This is the resistance presented by the triode to ac signal currents, and typical values range from a few hundred to over 100,000 Si. The transfer curves, relating input voltage and output current, are shown in Fig. 7.3(b). From the slope triangle shown we can define the transconductance J?„as A: -i (mhos) g. 5i£l... (7.4) Transconductance is the control factor for the output generator, as it was for the transistor. The magnitude ofg m for vacuum lubes will range from 1000 to over 40,000 //mhos. The product of the magnitudes is ^ " Wr A/, b Aw, or gm r . (7.5) (7.6) This shows that the three coefficients are related. A low-// lube will have a low plate resistance and a high-// tube will have a high plate resistance. 7.4 The Pentode In the triode we find a small capacitance C„ of 2 to 5 pF between grid and anode and a similar small capacitance between grid and cathode. At fre- quencies of I MHz or more in the common-cathode circuit, the reactance of '#*• Xc. = 1 2*/C„ becomes small enough so that it feeds back an appreciable current from the high signal voltage at the anode to the lower signal voltage at the grid. This feedback current causes instability of the circuit gain and possible oscillation. The use of the triode in the common-cathode circuit is therefore limited to the audio frequencies. This defect of the triode was overcome by adding two shielding grids between the control grid and the anode. Such a lube contains a cathode, a control grid G„ a screen grid C 2 , a suppressor grid C„ and the anode; the resultant five-element tube is called a pentode. The pentode is useful to frequencies of several hundred megahertz because C 2 and G 3 , as electrostatic shields, eliminate the capacitance between control grid and anode. A circuit symbol and a common-cathode circuit for a pentode are shown in Fig. 7.4(a). Triode Characteristics 151 \{ °2 (a) 20 15 1 .0 ==n A \\ 0.5 1.0 - 1.5 -2 3 -4 6 100 200 (b) 300 400 Figure 7.4 (a) Pentode in common-cathode circuit ; (b) output characteristics, 6EA8 pentode, V , = 125 V. Grid G z is maintained at ground potential for signal frequencies by the large bypass capacitor C,. A positive voltage is placed on G 2 , the screen grid, and this accelerates the electrons to a high velocity. Thus G z is able to accel- erate the electrons with its positive dc voltage but still serves as a grounded screen for signal frequencies. The suppressor grid C 3 is connected to the cathode so as to serve as another electrostatic screen between grid and anode. The high velocity electrons that pass through the openings in G 2 coast through Gj and reach the positive anode. The parameters for the pentode, //, g m , and r„, remain as defined for the triode. Because of the low slope of the output curves, the plate resistance is found to approximate 1 MQ. The anode current is almost constant with 162 The Vacuum Tube The Triode Common-Cathode Amplifier 163 changes in anode voltage for a given grid voltage and the pentode behaves as a current generator. In general, it is similar in characteristics to the FET. 7.5 The Equivalent Circuits In Chapter 3 we developed the idea of an h equivalent for any two-port circuit, and in Fig. 7.2 we drew the basic connections for a triode as a two- port element. Therefore, the h equivalent can represent the triode as in Fig. 7.5. For the //-parameter circuit we had Eq. 3.15 and 3.16: Vi-kfi+KY* (7.7) Iz - hfl> + KV X (7.8) and we can rewrite these equations with vacuum-tube quantities as V, = h,I c + h,V i„ - g m V. k + ^ (7.9) (7.10) That is, r p = \/h as the plate resistance and we previously showed /;,/, = SmVv Triode Figure 7.5 (a) //-Parameter model from Chapter 4 ; (b) equivalent circuit for the ideal triode; (c) pentode equivalent circuil. We reasoned that a negative grid attracts no electrons and so I c — for the triode. At low frequencies there is no feedback of voltage from output to input and so h, = 0. The input circuit is open and Eq. 7.9 is meaningless. Equation 7.10 represents the output circuit of the triode, as in Fig. 7.5(b). We have a load current /„, dividing into current VJr f through the plate resistance, and a controlled current source g m V, k , with its current dependent on the grid-to-cathode ac voltage V, k . The circuit in Fig. 7.5(b) represents the triode for ac and is the current-source equivalent circuil for the triode, as a small-signal linear amplifier. A pentode equivalent circuit is derived by the same procedure used for the triode. The current taken when values of r p exceed 500,000 Q is negligible, compared to the current taken in usual loads, however, and r„ may be dropped from the circuit with negligible effect. We have the pentode equiva- lent circuit in Fig. 7.5(c), for small signals at audio and low radio frequencies. The form of the equivalent circuits for triode and pentode is identical to the models previously developed for the bipolar transistor and the FET. 7.6 The Triode Common-Cathode Amplifier With the cathode as the common element we have the common-cathode triode amplifier in Fig. 7.6. We replace the triode with its equivalent circuit between G, A, and K in Fig. 7.6(b). Except for the notation, the circuit is M °2 I o — It © 2 (a) Figure 7.6 (a) Common-cathode triode amplifier; (b) equivalent circuit for (a). 164 The Vacuum Tube identical to those already analyzed for the bipolar transistor and the FET so we shall merely state the results of circuit analysis here. Voltage Gain The circuit yields (7.11) The negative sign indicates a 180° phase reversal between V, and V . Input Resistance The value of R t is usually made about 1 MQ and at audio frequencies the input of the triode represents an open circuit. Output Resistance We short-circuit V„ making V, = V ik = and the current source is then open (zero current). As a result, from the 2,2 terminals we see only K = r„ (7.12) as the output resistance of the amplifier. The common-cathode circuit is generally used for medium gain at audio frequencies. 7.7 The Pentode Common-Cathode Amplifier The pentode common-cathode circuit in Fig. 7.7(a) was generally applied because of greater gain and stable operation at radio frequencies. To main- tain stability the reactance of C, should be only a few hundred ohms at the lowest operating frequency. Capacitors C, and C and resistors R, and R, are parts of the bias circuits and are dropped from the equivalent circuit for the ac signal. Voltage Gain The equivalent circuit is simple and the voltage gain can be written as 4. = Y = s- R (7.13) Loads as high as 100,000 Q are used and gains of several hundred are obtained. The Cathode Follower 166 *V„ (a) (bl Figure 7.7 (a) Common-cathode pentode amplifier ; (b) equivalent circuit for (a). Input Resistance With R, E 1 Mil, the input resistance can be assumed to be an open circuit. Output Resistance Following the method used for the triode, we have /?„ = /•„ (7.14) and this is very large. The pentode common-cathode amplifier is generally used up to fre- quencies of many megahertz. A disadvantage of the circuit was the need for C, and R, in bypassing the screen grid to the cathode. Grid biasing may be done by any of the methods employed with FETs. 7.8 The Cathode Follower In the common-anode circuit or cathode follower in Fig. 7.8, we place the anode at ground for the signal but maintain it positive for acceleration of the electrons in the tube. Resistor R, is large and dropped from the equivalent circuit. Circuit performance is found to be similar to that obtained from the emitter follower or the source follower. Resistor R, may approximate 1 Mil. 156 The Vacuum Tube l°— K- I o- -02 lo- K* V„± »«• C fc *»"rfO -o2 lo- -I 2 (a) (b) Figure 7.8 (a) Cathode follower circuit; (b) equivalent circuit for (a). Voltage Gain From the output circuit we can obtain ' * m 'V, + R k Around the input loop and Substituting for V tk and rearranging, Clearing the denominator and dividing by r p , we have But usually /? t < /■„ and /?*/r p can be dropped as small compared to unity. Then we can determine the gain as A - V °- *■** ' V,~\ + gn,R„ (7.15) Since g„R k > 1, the gain is less than but near unity. One side of the output signal is at ground potential and this may be an advantage. Output Res/stance The output resistance at the 2,2 port is low and approximates The input resistance is very high. R, = j- (O (7.16) The Grounded -Giid Amplifier 167 The cathode follower acts as an impedance transformer, from a high input resistance to a low output resistance, as did the emitter follower and the source follower circuits. The circuit is usually designed with triodes since with only unity gain the high fi of the pentode provides no advantage and the pentode requires an expensive screen-cathode bypass capacitor. Grid bias is obtained as with the FET. Example: Find the performance of a cathode follower using a triode with H = 30 and r„ - 14,000 Q, R k - 3000 £1. We have ^=£ = Wo = °- 002,4mho With Eq. 7.15 we need g m R k = 2.14 x 10" 3 x 3 x 10 3 = 6.42 Therefore 6.42 A,= = 0.87 1 + 6.42 as the voltage gain. The output resistance is 7.9 The Grounded-Grid Amplifier The circuit in Fig. 7.9 is the groimded-gricl amplifier, similar to the C-B transistor amplifier. Grounding of the grid provides an electrostatic shield and reduces the transfer of energy between output and input circuits. The frequency range of the triode is extended to many megahertz by this circuit but the input resistance is low. Voltage Gain The voltage gain is A ' V = g„R l + gji. I ± and this is relatively low. We have assumed 1 + M = M- Output Resistance The internal resistance factors of Eq. 7.17 lead to Ro = r,(\ + g m R.) (7.17) (7.18) 158 The Vacuum Tube R 5 K. (a) (b) Figure 7.9 The grounded-grid amplifier. Input Resistance The input resistance is conveniently written as and this is a small resistance. The circuit provides an impedance transformer of low gain, operating from a low input resistance to a high output resistance. Again, a pentode offers no gain advantage; when used the grids are connected together giving the characteristics of a high-// triode. Example: With g m -- 2500 //mhos, r p = 18,000 £2, R, = 500 £2 and R = 4000 Q, find the gain and resistances when this triode is used in a G-G circuit. By Eq. 7.17, 2.5 X 10" 3 x 4 x 10' A.= 1 + 2.5 X 10-' x 500 + (4 x 10 3 )/(18 x 10 3 ) 10 2.47 -4.05 By Eq. 7.18, By Eq. 7.19, R„ = 18 x 10 3 (1 + 2.5 x 10" 3 x 500) = 40,500 a R ' /■ i 4000 \ ' 2.5 x 10 J V ' 18,000,/ = 489 ft The Cathode-Roy Tube 159 These values confirm the statements made concerning the relative magnitudes of the input and output resistances. 7. 10 The Cathode-Ray Tube The cathode-ray lube is a vacuum-tube device used for television viewing and as a laboratory instrument for visualization of electrical voltages and cur- rents in circuits. It is built in an evacuated glass envelope and employs electron-beam deflection by electric or magnetic fields that vary with the signals applied. The tube includes an electron-emitting cathode and beam- focusing electrodes in an assembly called an electron gun, followed by two pairs of mutually perpendicular deflecting plates and a fluorescent viewing screen. When magnetic field deflection of the beam is used, one set of deflecting plates is replaced with a pair of coils, producing a magnetic field. A visible spot of light is produced at the point of impact of the beam on the screen; the color of the light is dependent on the fluorescent material with which the screen is coated on its interior face. A cathode-ray tube is dia- grammed in Fig. 7.10(a) and (b). The accelerating potential V a increases the beam velocity and brightens the spot of light. The velocity of the electrons is very high; upon impact, Electron Gun A, Deflection Plates - P Screen t D Screen <b> Figure 7.10 (a) A cathode-ray tube; (b) deflection system. 160 The Vacuum Tube part of the electron energy is converted to visible light and part to heat on the screen. A stationary spot can cause a burn on the screen. The geometry of the deflecting plate system in Fig. 7.10(b) can be used to determine the deflection D on the screen as (m) (7.20) With two pairs of plates at right angles, the position of the spot can be moved in both x and y axes on the screen. More usually a sweep voltage, which increases linearly with time, is applied to the .v deflection plates. A voltage applied to the y deflection plates will then appear as if plotted against time. The complete formation of a sine wave on the screen is shown in Fig. 7.1 1, for one sweep. By use of a sawtooth form of sweep voltage, as in Fig. 7.12, the figure can be repeated. Screen Sine Signal on | 2 y Plates Figure 7.11 Plotting of a sine wave against a linear sweep voltage. In television, one set of deflection plates is replaced with a pair of coils producing a magnetic flux density B, perpendicular to the electron beam. The deflection is that of a magnetic field on a current and is £L- (m) (7.21) j_Ll m B For a given deflection we can use higher acceleration voltages and obtain brighter spots with magnetic deflection. Materials used for the fluorescent screen have varying properties of light persistence after bombardment by the electrons. We have screens with image Review Questions 161 persislence in microseconds to screens with image persistence measured in minutes. Various colors are also obtainable, with green or blue common in laboratory equipment, and the three basic colors available for color television screens. Figure 7.12 A sweep waveform. 7.11 Comments Because of its broad frequency range and high gain, the pentode was once widely employed as a voltage amplifier. Triode use was confined to audio frequencies or for impedance transformation when used as a cathode fol- lower. The grounded-grid circuit still finds some application in high-power transmitting equipment. Transistors are now generally used, however, because of the advantages previously listed. REVIEW QUESTIONS 7.1 Explain what is meant by V BB , V C a V^ l b , /„ i b , V, k . 7.2 Explain how the grid controls the passage of electrons through a triode. 7.3 What happens if a vacuum tube is operated with a positive grid? 7.4 What amount of power is dissipated in the triode in Fig. 7.4(b) with a Q point at V c = -1.8 V, V b = 150 V? (Interpolate the curves.) 7.5 If the maximum allowable P d 2.5 W for a triode, would a Q point at V b = 250 V, V e -- -I V be desirable for the triode in Fig. 7.4(b)? 7.6 What boundaries would you select for the placement of a Q point on the curves in Fig. 7.3(a) for distortionless amplification? 7.7 Define ft, g„, and r p . How are they related? 7.8 Triode A has a wide-spaced grid, tube B has a close-spaced grid. Which has the highest /*? Which has the highest r p ? Could you determine £ m ? 7.9 What can you say about current amplification in a triode? 7.10 What happens to the anode current if a triode is operated with a grid bias more negative than — V BB ln"> 7.11 Why do we add extra grids to form the pentode? 162 The Vacuum Tube 7.12 Why is a penlode said to be a current source? 7.13 How do we accelerate the electrons through the screen grid? 7.14 Why do we use bypass capacitor C, with the pentode? 7.15 How large should C, be? Why is the value of C, determined at the lowest fre- quency of interest? 7.16 Why would you select a cathode follower in place of a common-cathode cir- cuit? 7.17 List the similar types of amplifiers, using bipolar transistors, FETs, and vac- uum tubes. 7.18 Name two reasons for use of a grounded-grid amplifier. 7.19 What condition must be assumed to justify -g m R as the gain of a pentode common-cathode amplifier? 7.20 Why does the grounded-grid circuit operate with stable gain at many mega- hertz? PROBLEMS 7.1 For the iriode in Fig. 7.3, plot curves of anode voltage on the ordinate and grid voltage on the abscissa, for several values of constant anode current. Measure AvJAv c ; what is this parameter called? 7.2 The triode in Fig. 7.3(b) is biased to a Q point at l b = 1.5 mA, K c = -4 V. What is the peak value of a sine-wave signal that can be used without driving the grid into the positive region? In terms of operating within a small region of the curves, would this sine voltage really be a small signal? 7.3 What is the // of the Iriode represented in Fig.7.3(a) in the region near v b = 250 V, i b = 1.5 mA? 7.4 The transconductance of a triode is 4000 //mhos and ft is 8. The grid voltage is kept constant; find the increase in anode current when the anode voltage is changed from 200 to 235 V. 7.5 An equation for the output curves of a triode is i„ = K(Sv t + v b ) (mA) At »•» = 200 V and v, - - 12 V, the current is 6 mA. (a) What is the current at v„ = 300 V and v c = —8 V? (b) What v c is needed to return i b to 6 mA at v b 300 V ? 7.6 Taking A changes in voltages, determine fi,g m , and r„ for the triode described by Amp, i b - 38 x 10-*(f 4 I 8i' c ) near v b = 200 V, v c = - 12 V. 7.7 The triode of Problem 7.6 has an anode current which is to increase 0.3 mA when the grid voltage changes from -2 to -3 V; what change in anode volt- age must be made simultaneously? Problems 7.8 From the following data taken on a triode, find // and g m : 163 i» (mA) «c v b 8.2 165 6.0 130 6.0 -1 165 4.1 -1 130 4.1 -2 165 7.9 A pentode has r p = 650,000 ft, g m 2500 /zmhos. What is the value of //? What load R should be used to obtain a voltage gain of 120 in a common- cathode circuit? 7.10 For the pentode in Fig. 7.4(b), determine graphically the value of r„ for v c = -1.5 V and the value of g m near v b = 200 V, i? c = -1.5 V. What is the value of/*? 7.11 For a certain triode with g m = 3300 //mhos, r„ = 5100 £2. (a) Find the anode current change produced by variation of the grid-cathode voltage from -2 to -6 V, at v b = 140 V. (b) What change in anode voltage will bring the anode current back to its original value, with v c = —6 V? 7.12 A common-cathode circuit uses a triode with r p = 4000 £2, n — 8, and input signal V, = 2 V rms, ac. Find the output rms voltage across a 5OO0-£2 load. 7.13 Starting with Eq. 7.15, derive a gain expression for the cathode follower in the form r P + flR k 7.14 In the cathode follower in Fig. 7.8, R k = 1000 SI, g m = 0.003 mho, and fi = 25. If Vi = I V rms, find the output rms voltage. Also find the output resis- tance. 7.15 A pentode has g m -- 0.0035 mho, r p = 650,000 Q and is used in a common- cathode amplifier to provide 35-V output when the input signal V, = 0.05 V rms. What value of R is being used? 7.16 A grounded-grid amplifier uses a triode having fi ■ -- 70, r p = 40,000 CI. With R, = 300 fi, R - 10,000 £2, find the voltage again and the input and output resistances. 8 Frequency Response of RC Amplifiers We have been assuming that the series capacitors in amplifiers are infinite and the shunt capacitances of transistors and tubes are ideally zero. A prac- tical amplifier uses nonideal capacitor values, however, and the effect on the operation is dependent on the reactance of the capacitors that varies with frequency. When we use multistage cascaded systems for greater overall gain, the frequency effects are compounded. The frequency response of amplifiers will be studied here in terms of the very commonly applied resistance-capacitance (RC) amplifier. 8. 1 Cascaded Amplifiers Figure 8.1 shows a typical RC transistor amplifier of two stages, from A, to A 2 and from A 2 to A 3 . These stages may be analyzed separately, with the overall gain determined as the product of the individual stage gains. Output V 3i is K« = -A,.,V 22 (8.1) and V2i=-A,y u (8.2) Then by substitution for K 22 , we have y 3 2 = (-A„K-A„)y u The Amplifier Passband 165 Figure 8.1 Two-stage RC amplifier. and the overall gain between port 1,1 and port 3,3 is A — ^» a A 'II (8.3) and in general ^.(ov) = A„A„A„ . . . (8.4) We have previously shown that when the individual stage gains are ex- pressed in decibels, then the overall gain is obtained as the sum of the in- dividual decibel gains: dB, /<„,„.> = A vltn + A„ 1B + A, UB + •■■ (8.5) 8.2 The Amplifier Passband We usually wish the output waveform to be the same as the waveform at the input to the amplifier and that the distortion be negligible. However, our amplifier input signal may consist of many frequencies distributed over a wide frequency band. For instance, a l-fis pulse signal contains frequency components of which those to 4 MHz arc important if we are to obtain an accurate reproduction of the input waveform. To have an undistortcd waveform, we must amplify all frequencies equally. If this is not done, we have frequency distortion in the amplifier. Amplification of the pulse to I MHz will produce a distorted, but recognizable, pulse form. If we plot the performance of an amplifier as a gain versus frequency curve, ideally an amplifier should have a curve that appears as a horizontal 164 168 Low Frequency Response of ftC Amplifiers High 0.707 A ■ulroid) V (mid) *angc J i Bandwidth h Range Mid Frequency ^ "V / i i i l \ 10 I00 I000 I0 4 10 s I0« /(Log Scale) (a) '(> (mid) -0.707/1 U "lii.ll 10 100 103 (b) I0 4 105 Figure 8.2 (a) Gain-frequency plot for an RC amplifier; (b) plot for a direct- coupled amplifier. straight line over the desired frequency range. More practically, we obtain a curve like that shown in Fig. 8.2(a). We have been assuming that blocking capacitor C c will have sufficient capacitance to be a negligible series reactance in the equivalent circuit. Such capacitors must have reasonable cost and size, however, and there will always be some range of frequency from zero upward in which the blocking capacitor is too small to meet the ideal requirement, and represents an appreciable reactance. This is the reason for the fall in gain in the low- frequency range in Fig. 8.2. Also, we have been assuming the maximum frequency of the signal to be low enough that the very small internal capacitance of a transistor or tube and the stray mounting and wiring capacitance represent such high reactances as to be considered an open circuit to ground across the input or load resis- tances. There is, however, always some frequency above which these react- ances have an appreciable effect in shunting the load. This accounts for the fall in gain in the high-frequency range in Fig. 8.2. Only in the mid-frequency range arc we able to satisfy the assumptions on both series and shunt reactances and consider them negligible in effect. In this mid-range of frequency we obtain the predicted gain figures of the preceding chapters. The low-frequency range and the high-frequency range are almost always well separated in frequency and quite distinct, as in Fig. 8.2. We are able to analyze the amplifier response in each region independently and to determine and evaluate the circuit factors responsible for the fall in gain. The Frequency Plot 167 We arbitrarily bound the mid-frequency region of uniform gain by choos- ing limit frequencies,/, and/,, at which the gain has fallen to 0.707 or \/«J~T of its value in the mid-frequency region. These frequencies are called the cutoff, band-limit, or half-power frequencies. At/, and/ 2 the output power is one-half of the mid-range output. That is, and At/, or/j, and the power is V. = A, P -VI . *mld — -V? - (mid) V l R R (8.6) V'„ = 0.707/4 ■■(mid) P _ (V'o) 2 _ [0.707^ B(miJ ,K,]' _ 0.5M. <aM> KJ» (8.7) We see that Pt*-*5r*m ( 8 - 8 > as predicted for the band-limit frequencies. The amplifier passband is defined as the mid-frequency region, with a bandwidth given by bandwidth (BW) =/ a — /, (Hz) (8.9) A direct-coupled (DC) amplifier omits C c and its low-frequency response extends to zero frequency. It still has a high-frequency region due to the inherent capacitances of the transistor or tube. The gain-frequency curve appears in Fig. 8.2(b). In deciding to neglect one resistance or reactance as large or small with respect to another, sufficient accuracy is usually obtained if there is a ratio of 10:1 in the respective impedance magnitudes. For example, a resistor of 1000 Q is in parallel with another of 10,000 fi. The combined resistance is R 10 3 X 10 4 _ IP 4 " L x 10 3 |- 10 x 10 3 II X 10 3 = 9I0Q If we drop the 10,000-Q resistor from consideration as large with respect to the 1000-Q resistor, we are saying that we have a resistance of 1000 £2 in- stead of the actual 910 Q. This error is less than 10 per cent and can usually be overlooked because of the larger circuit variations introduced by the parameters of the transistors and tubes. 8.3 The Frequency Plot The frequency axis of a gain-frequency curve is usually plotted on a loga- rithmic scale. In this way each multiple of 10: 1 in frequency is given equal distance on the abscissa and a very large frequency range can be covered, 168 Frequency Response of RC Amplifiers BuiulwKlth J_ J. I0 5 I0 ft I0 3 \Q* Frequency (Hz) Figure 8.3 A gain plot in decibels. as shown in Fig. 8.3. Each multiple of 10: l in frequency is called & frequency- decade. The mid-frequency gain does not vary with frequency and can be used as a standard. By comparing the low- and high-frequency gains to the mid- range gain, we can obtain a general gain-frequency curve, said to be nor- malized on the mid-frequency gain. To normalize a gain figure, we divide by the mid-frequency gain, to give terms such as ■^i'(lo) . A,i M \ *r(mMl Mrnld) The value of these ratios in the mid-range is unity for all amplifiers and so the gains are normalized to l. The normalized gain figures are ratios and can be converted to decibels, as -, dB-20log (8.10) •"►(mid) | ^»i(mlJ> In the mid-frequency range the ratio is 1 and the logarithm of 1 is so that when stated in decibels the normalized mid-frequency gain is OdB. At the limit frequencies we have 20 log (0.707) = -20 log (1.414) = -3dB and so the limit frequencies are correctly called the — 3-dB frequencies. A normalized gain-frequency plot in decibels is drawn in Fig. 8.3. The phase angle of A ft „ m for a single C-E stage is 180°. Normalizing of A ctM and A v(bl) against A, imli) will result in their phase angles being normal- ized against 180° as a reference angle. The total phase shift will then be 180° -r- 0,„ and 180° - hl . At low frequencies the total phase shift tends toward 180° + 90° - 270° at zero frequency. In the high-frequency range, the total phase shift tends toward 180° — 90° = 90° at a very high frequency. 8.4 Low-Frequency Response The most commonly used amplifier is the /?C-coupled, common-emitter circuit of which Fig. 8.1 is an example. The purpose of each of the circuit elements should be understood since the four-resistor bias network is em- Low-Frequency Response 169 ployed for each transistor. As drawn, the circuit is too complicated to be readily analyzed and we break it down by stages for better understanding. For this purpose we consider stage 1 as between A, and A* and redraw that part of the circuit in Fig. 8.4(a). We assume that C E is large and represents a negligibly small reactance so that we can drop R E and C B from the equivalent circuit. The effect of an unbypassed R E will be considered in Sec. 8.7. We replace the transistor Q x with its equivalent circuit, the input resistance h,„ and the current generator fcKfc. We previously showed that the effect of R, and R 2 could be replaced by a single resistance R B , where R B = *'*» R, H R 2 and R B appears in the circuit in Fig. 8.4(b). By proper bias circuit design, however, we can choose R, and R 2 so that R B ^> R h where R,, is the input resistance of the transistor, usually /»,,. The equivalent circuit in Fig. 8.4(c) follows after dropping R B . CO Figure 8.4 (a) One stage of the RC amplifier; (b) partially simplified; (c) equivalent circuit at low frequency. 170 Frequency Response of RC Amplifiers Wc first write the mid-range gain by assuming the reactance of Q. neg- ligible compared to /?,,; this is really the definition of a mid-range frequency, with capacitor C c represented as a short circuit. Then Vzz = -g m V»- RR ii_ (8.U) (8.12) •R + R„ Then the mid-range gain for the first stage is a V 22 _ a A A,. " mW) ~ V bt - g "R + R„ We now reinsert C c and derive the low-frequency gain for the circuit in Fig. 8.4(c). The output K 22 is V^^ = ~IiR(, and we need to find / 2 as a portion of the transistor current g„V hc . Figure 8.5 The current divider example. This question can be resolved by use of the current-division factor. In Fig. 8.5 the voltage across the parallel branches is equal and so we can write the equations RJl* V=R b l, - R„ I R„ In Eq. 8.13 we cancel R„ on each side and the branch current is I\ = Likewise, with Eq. 8.14 we obtain R. + R» R. / (8.13) (8.14) (8.15) (8.16) R„ + R> The current /, divides out of / in proportion to R b , the resistance of the other path divided by the sum of the resistances R, + R b . Similarly, / 2 divides out of / in proportion to /?„, the resistance of the other path, divided by the sum of the two resistance paths R„ + R b . Equations 8.15 and 8.16 demonstrate the use of current-division factors. Low-Frequency Response 171 Wc now write the reactance of C c as x =-L-= ' c caC c 2nfC c using co = Inf. The impedance of the A path is then Accordingly, with R as the resistance of the other path and R — /?,, — (jloiCc) as the impedance of both paths, we have current / 2 as a fraction ofg m V><: (8.17) (8.18) R + R„ ~ UlcoC c ) Dividing out R + R h , we have /. = g m Y>. r r i R + R, \-j 1 As a magnitude, this is h = g m v> The output voltage is coCrAR + RJ. 1 Vzz = -IiR„ = -g m V» V + lcoC c (R + R„)j I 1 (8.19) (8.20) R 4 R, y l + IcoCrAR + /?i,) J Dividing out V b „ we find the low-frequency gain as 1 A V " - c RR » "rtlrt - y^ ~ 8m R ., ^ V 1 + LcoCciR + R„)\ (8.21) LcoC c {R -r R„) Comparison of the multiplier term with Eq. 8.12 shows that the multiplier is ^„( m , d ). Then the gain ratio is ^•(lo) 1 (8.22) *»<rald) (8.23) V 1 + IcoCcAR + R„)i There is an associated phase angle: » = aa - < cJ + RJ in addition to the 180° phase shift in A r(mU) . The effect of frequency on the gain is shown by the radical in the de- nominator of Eq. 8.22. If/= 0, co = 2nf = 0, and the second term in the radical becomes infinite, the gain is zero, with a phase angle of 180° — 90° 172 Frequency Response of RC Amplifiers = 270°. As frequency increases, the second term in the radical decreases with respect to I and the gain ratio increases toward the mid-frequency value of unity. 8.5 The Low-Frequency Limit Let us examine the situation when the terms in the radical of Eq. 8.22 become equal; that is, at /, 1 - „ ,„ ,*. . „ , (8.24) Then we have 2nf x C c {R | R„) A, m. = I V2 = 0.707 (8.25) ^Hmld) ^/l -f 1 We see that the frequency defined in Eq. 8.24 is the lower limit frequency of the amplifier. Frequency/, is associated with the circuit elements chosen by the designer as fl = 2nC c (R + R„) (8 " 26) The lower limit frequency is dependent on the size of the blocking capacitor and the resistances through which it charges. These are factors that the designer can select to place the cutoff of the mid-frequency region where cost of parts and size considerations permit. We can substitute this value of©, = 2nf t into Eq. 8.22 and 8.23 to ob- tain a general expression •"»(io) L with a phase angle = taEr'4 (8.27) (8.28) These expressions are important results. Any amplifiers having the same product of blocking capacitance and charging resistances will have the same frequency response. That is, a small capacitance associated with large resistances or a large capacitance with small resistance values can lead to the same limit frequency. A general curve for the low-frequency response of all RC amplifiers is plotted in Fig. 8.6, from the decibel values of Table 8.1, which is calculated from Eq. 8.27 and 8.28. To use the curve, one need merely know the/, frequency for a particular amplifier and the response at other frequencies is readily found. In order to show the gain increasing with frequency as a normal low-frequency response, the curve is plotted in terms of f/f,. Figure 8.7 is the general phase response. The Low-Frequency Limit 173 dB Limit Frequency / Mid t Range ^v (mid > /S / 20 Slope: - 20 dB/Decade 30 Jill I I MM I I I III 0.05 0.I 0.2 0.5 I.O 2 5 10 20 Figure 8.6 Low-frequency response in decibels. TABLE 8.1 Low-Frequency Response from Eqs. 8.27 and 8.28 Phase Angle Total Phase /.// an dB (degrees) Angle (degrees) 10 0.1 -20 + 84° 264° 5 0.2 -14 79° 259° 2 0.5 -7 63° 244° 1 1.0 -3 45° 225° 0.5 2 -1 27° 207° 0.2 5 -0.2 IT 191° 0.1 10 -0.04 6" 186° "Including the inherent 180° phase shift of a C-E amplifier at mid-frequency. The table and curve show that for a 1:10 change in frequency (I decade), at low frequencies, the gain changes by 20 dB. It is hardly necessary to plot the curve below 0A/lf, because we know that Ihe gain varies at 20 dB per decade and W dB 0.1 0.01 0.001 -20 -40 -60 174 Frequency Response of RC Amplifiers 100° 80° 60° 40' 20 c C 1 1 1 1 II 1 iTiT 0-1 0.2 0.5 10 20 .0 2 5 fff, Figure 8.7 Phase angle variation ai low frequencies. The expression of Eq. 8.27 can be plotted for any amplifier by drawing a horizontal asymptote at dB for frequencies above/=/, and a sloping asymptote falling 20 dB per decade below f = f,. At/ = /,, the limit fre- quency gain is plotted at — 3 dB. The response can then be sketched through the — 3-d B point to the asymptotes. Example: The first-stage circuit in Fig. 8.1, between A, and A 2 , has C c = 0.5 /xF, R -= 5 kQ, and a transistor with h lt »■ 900 Q. Since r> R i*z 10 X 10 3 X 10 X 10 } _ Q ,nnr» K " ~ rTTrI ~ no x io' yiuu " this resistance can be neglected with respect to h lt at 900 Q, and R,, = h„ 'U(lo) A ri iiu.l i dB 5 10 - 15 20 - 25 Limit V Fi equency \ -dB Pom / Slo )c: A i i i 20 dB Decade i i i i i i 1 L_ 20 100 200 500 50 /(Hz) Figure 8.8 Response plotted for the example. Low-Frequency Response for the F£T and Vacuum- Tube Amplifiers = 900 £1. Then 175 /,= I I 2nCc(R + /?,,) 6.28 x 0.5 x 10 6 X (5000 | 900) 1 O.OTs? = 54 Hz This is the band-limit frequency. The result is plotted in Fig. 8.8, by use of the asymptotes and the — 3-dB point at/,. 8.6 Low-Frequency Response for the FET and Vacuum-Tube Amplifiers In Fig. 8.9(a) we show an FET amplifier using a four-resistor bias circuit. We assume that C s is large and adequately bypasses R s so that the com- bination can be dropped from the equivalent circuit in Fig. 8.9(b). We again have R.= _ Mi Ri /?, Comparison of the equivalent circuit of the FET amplifier with that for the bipolar transistor in Fig. 8.4(c) shows the circuits identical, except for some of the resistor designations. Therefore the low-frequency analysis of Sec. 8.4 and 8.5 applies to the FET. We need note that the limit frequency for the mid-frequency region of the FET amplifier is written I /.= 2nC c (R + R B ) (8.29) As a rule R + R n is much larger than for the bipolar transistor and the needed value of C c will be reduced for the same/, frequency. Figure 8.10 shows a pentode amplifier with its equivalent circuit. Once more we compare the equivalent circuit with Fig. 8.4(c) and see that it is identical to that analyzed for the low-frequency response of the bipolar transistor. For the pentode the limit frequency will be written /. = 1 2nC c (R | R K ) (8.30) and all the universal gain and phase curves apply with/, as the limit fre- quency for the mid-range of the pentode amplifier. Example: Typical values for a pentode amplifier would be R — 50,000 £2, R„ - 500,000 $2, and g m = 0.0035 mho. Find the value needed for C c to make/, = 54 Hz as in the example of Sec. 8.5 and find the mid-frequency and/, gains. 176 We have Frequency Response of RC Amplifiers V DD Cr (~)*o W* m> «il v n i \2- Rts n ■ (a) Figure 8.9 (a) FET amplifier; (b) equivalent circuit. /■ = 1 2nC c (R -| R,) and R \ R, = 50,000 + 500,000 = 0.55 x IO 6 SI. Then with /, - 54 Hz, we have C 1 c ~ In X 54 x 0.55 X 10 6 = 5.36 X 10-» = 0.00536 x IO" 6 F = 0.005 /zF This is much smaller than the value of C c = 0.5 jxF needed to give the same limit frequency for the bipolar transistor. The voltage rating required for the 0.005 ftF capacitor in the pentode circuit may be 300 V and that for the bi- polar transistor may be 15 V, however, so that costs and size may not differ appreciably. The Unbypessed Emitter Resistor 177 (b) Figure 8.10 (a) A pentode amplifier; (b) equivalent circuit. The gain at mid-frequencies is 0.0035 x 5 x 10* x 0.5 x 10 6 0.55 x 10 6 = 159 The gain at /, = 0.707 X A,, mW = 0.707 X 159 = 112. 8.7 The Unbypassed Emitter Resistor While we have assumed the emitter bypass capacitor C E to be of sufficient capacity to bypass R E adequately, the capacitor is not often used, for reasons of space and cost. Then we have the C-E amplifier input circuit as in Fig. 178 Frequency Response of RC Amplifiers 'c The Unbypassed Emitter Resistor 179 (a) (b) Figure 8.11 (a) Unbypassed emitter resistor; (b) equivalent circuit. 8.11(a). The input circuit equation is V, = /»„/* + (/ 4 + I C )R E (8.31) Since l e = A /c / & , we have the input resistance R, as R, = jf = K + (I + h,.)R E = *<< + hf,R E (8.32) The input circuit is drawn in Fig. 8. 1 1(b), as part of the usual transistor equi- valent circuit, and consists of/;,, in series with a large resistor h f ,R B . Actually, this is the input circuit of a C-C amplifier. We have and ht, + h [t R t V -hi "it* i V " ~ Kh ~ h,. + h,jt E v, v, (8.33) 1 + &R, + iJt* The load voltage is V = — g m RV bt and substitution of Eq. 8.33 for V h , gives 1 y. = -g m Ri ■v, i + g m R B But the term -g m R is recognizable as A v{mU} and so with R E in the circuit we have a gain designated as A',: A' — l-£ — A 1 K, -».«-«*» l+ gm R B (8.34) The gain is reduced by the presence of R E . Similar expressions are obtained for the gain with an unbypassed source resistor R s for an FET or for an unbypassed cathode resistor R K for a tube, used in the circuits in Fig. 8.12. When these bias resistors are not bypassed, the gain expressions of the preceding sections are multiplied by the factor 1/(1 + g„R E ), or equivalent, derived above. Using appropriate g m and resistance values, this factor is the same for all three active devices. The gain reduction is often made up by additional gain elsewhere in transistor circuits since the cost and space requirements for the bypass capacitor are excessive. With the relatively expensive and bulky vacuum tube, the extra gain was more costly and the bypass capacitor was commonly employed. 'DO -02 l o- S R s I o- -°2 t n a + ^ o°» v» ■s 5 K< |o » s4 —< (a) (b) oi o2 (c) (d) Figure 8.12 (a) and (b) FET with unbypassed source resistance; (c) and (d) triodc with unbypassed cathode resistor. 1 80 Frequency Response of RC Amplifiers 8.8 High-Frequency Equivalent Circuits; the Miller Effect The internal shunt capacitances of transistor and tube become small react- ances that cannot be neglected at some high frequency. A modified equi- valent circuit for the three devices is the result. For the junction transistor, the effect of the capacitances is illustrated by use of the hybrid-n equivalent circuit shown in Fig. 8.13. Capacitance C b , holds the charge stored in the base and is of many picofarads. Capacitance C bc is that of the depletion region at the reverse-biased base-collector junc- tion and is only a few picofarads. Resistance r , — \jh ot is large and eliminated in the equivalent circuit as we have done before. Figure 8.13 Hybrid-n transistor circuit. Figure 8.13 shows the capacities in the input circuit. The currents add at *as /, + /» = /, where (8.35) h = * = <oc te (y -v bt ) But V„ = A v V b , and we substitute, giving U = °>C bc (A v V bt - V bt ) = coC be V bt (A,- 1 ) (8.36) Substitution of I, and /, into Eq. 8.35 yields /,=/,- I z = <oC b .V bt - o>C bc V bl (A v - 1) Since A v = —g m R for the C-E circuit, the terms can be combined to give /, = o>V bt [C b , + (1 + g m R)C be ) (8.37) Current /, passes into an apparent input capacitance Q. - C„. + (1 + g m R)C bc (8.38) High-Frequency Equivalent Circuits; the Miller Effect 181 This capacitance is the result of a multiplied value of C bc , moved into the input circuit in parallel with C bt , between B and E. The effective value of C„ is much larger than either C bc or C b , and this multiplying of capacitance is called the Miller effect. We then have the two branches of the input circuit in Fig. 8.14, which is the high-frequency g m model of the transistor. For a given l b the voltage V b , will fall as the reactance of C lr falls with frequency. Therefore, the input capacitance C lt is responsible for the reduction of gain of the transistor amplifier at high frequencies. B o- lc 'I... 9lC k C -o Qg m y„r E E Figure 8.14 The high-frequency g m model. The FET has a capacitance C„ from the gate to the source through the insulating layer of a MOSFET or the depletion region of a JFET. The FET also has a capacitance C, d between gate and drain which includes the capaci- tance to the mounting of the transistor. These capacitances are usually in the range of I to 5 pF. The input circuit of the FET is drawn in Fig. 8.15(a) and is seen to be identical to the branched capacitances of the junction tran- sistor in Fig. 8.13. The FET, of course, has no equivalent of A,,. We could perform an analysis similar to that of Eq. 8.35 to 8.38 and would find that the capacitances of the FET can be represented by a single shunt capacitance C„ - C„ + (1 + g m R)C, d (8.39) much larger than C, d alone. The Miller effect also appears with the FET and the high-frequency model for the FET is that shown in Fig. 8.15(b), ■*d + / 1 D + •R i i t D + + Cvi (a) (b) Figure 8.15 (a) Capacitances for the FET; (b) high-frequency FET model. 182 Frequency Response ol RC Amplifiers with C,f in shunt to the input terminals. At high frequencies the input im- pedance of the FET is not infinite but falls as frequency increases due to C lf . With a driving voltage source having an internal resistance, the current taken by C lf reduces the value of V„ with increasing frequency and the gain falls. We might carry through the same reasoning process with the triode or pentode in Fig. 8. 16. We find a Miller-effect capacitance across the grid- cathode terminals as C„ - C t * + (I + g m R)C„ (8.40) We have a high-frequency model for the vacuum tube as in Fig. 8.16(c). The capacitance C„ is responsible for the fall of gain with increasing frequency as for the FET. Again, our three active devices operate in an equivalent manner. Example: A junction transistor has C bc = 4 pF, C b , = 60 pF, and g m = 4 mA/V = 0.004 mho and the amplifier load is 10,000 Q. Find the input capacitance C, c . First g n R = 0.004 x 10 4 = 40 Using the relation of Eq. 8.38, C u = C b , | (1 + g m R)C ic C„ - 60 + (! -r 40) x 4 = 220 pF l >"->< -\ A G — l- >< c«* A C c— („--■- QgnV* A -o K K (a) (b) ( C ) Figure 8.16 (a) Capacities in the triode; (b) circuit of capacitances; (c) high- frequency vacuum-tube model. 8.9 High-Frequency Response In the high-frequency range of an amplifier the series blocking capacitors represent zero reactance; this is also true for C e bypasses for the emitter resistors. But the internal C, capacitances of the active devices appear in shunt and we draw the first stage, A, to A lt from Fig. 8.1 in the high- High-Frequency Response 183 'b { (a) (b) Figure 8.17 (a) Stage 1 of the amplifier of Fig. 8.1 ;(b) high-frequency equivalent circuit. frequency g m model in Fig. 8.17. Resistance R t , is the input resistance of Q lt normally expected to be h le , and C„ is the Miller-effect capacitance of Q z . The gain of the C-E amplifier is A v = -g m Z„ where Z„ is the parallel impedance of R, and R h and the reactance of C„. This parallel impedance has a magnitude RR,. Zpl J(R + R __RR Jl _ 1 R + R,. The voltage gain in the high-frequency range of the amplifier is <4« (hi) _ gmRR, which has a phase angle (8.41) (8.42) (8.43) The first term of Eq. 8.42 is the mid-frequency gain of the amplifier, ^rtaid). however, and so ■^r(hl) — -^i'(mia) — , . „ „,. . ? (8.44) The gain ratio follows as ''ilnildl (8.45) 184 Frequency Response of RC Amplifiers The term in the parentheses in the radical increases with frequency /and the high-frequency gain falls. When the terms in the radical are equal, 2nf 2 C lr RRi, _ | R + R„ we find the upper limit frequency f z as (Hz) (8.46) InCuRR,, R + R„ The upper band-limit frequency is dependent on the product of C u and the parallel value of the associated resistances. The frequency response of the amplifier is established as soon as the values of C„, R, and R,, are chosen by the circuit designer. Using/ 2 from Eq. 8.46, we can write the gain ratio in the more general form -^M- = ' (8.47) ^m VI + (//A) 2 with a phase angle * = tan-(-Z) (8.48) The frequency response in Fig. 8.18 is the general response curve for Eq. 8.47 in decibels; the curve in Fig. 8.19 shows the phase response from Eq. 8.48. Knowing the component values that produce a given f 2 frequency, the response curve can be plotted by use of a few points selected from the curve or values from Table 8.2. dB - 10 Av ''U0.it Imuli - 20 -30 1 „ Limil S. Fre quency ^ \ A Slope: \ 20dB/de :aae ' \ ! ' ' 1 ' 1 1 1 1 . L . 1 | i i i i i 0.05 0.1 0.2 0.5 1.0 m 10 20 Figure 8.18 High-frequency response in decibels. The Frequency Limit of the Transistor 20° "40° 60° 80° 100° 185 : i i i i i i I i I i i i I... 5 10 20 0.I 0.2 0.5 l.O 2 Figure 8.19 Phase angle variation at high frequencies. TABLE 8.2 High-Frequency Responses from Eqs. 8.47 and 8.48 flh Decibels (gain) Phase Angle (degrees) Total Phase Angle* (degrees) 0.1 -0.04 -6° 174° 0.2 -0.2 -11° 169° 0.5 -1 -27° 153° I -3 -45° 135° 2 -7 -63° 117° 5 -14 -79° 101° 10 -20 -84° 96° •Including the inhcrenl 180° phase shift of a C-E amplifier at mid-frequency. The behavior of the amplifier at high frequencies is the inverse of the behavior at low frequencies when frequency ratios are used; that is, at 0.5/, the gain is the same as the gain at 2/ 2 , using the mid-frequency gain as a reference. At higher frequency ratios the gain continues to fall at the rate of —20 dB per frequency decade. 8. 10 The Frequency Limit of the Transistor Common-emitter current gain h fl falls at high frequencies, primarily because of the internal capacitances represented by C,,. If we use h ft0 as the usual gain figure at low or mid-frequencies, then h f , at any frequency is given by 186 the relation Frequency Response of RC Amolitiers */.= yr 1x^_ Wf,Y (8.49) When compared with Eq. 8.47, the form of this equation indicates that f=f„ is a limit frequency or -3-dB frequency for the transistor, at which By definition, h fl is the current gain for a short-circuit load, as in Fig. 8.20. With R = 0, the Miller-effect equation is C„ = C h + (l+ fc x?)C fc = c 4 , + c„ l "^ This equation also comes from the circuit, Fig. 8.20, since C bf and C bc are placed in parallel by the short-circuit load. if /„ + ii V »r i r* i '■Ct, C J «m "'ir L ° ' Shorl Circuit Figure 8.20 The transistor at high frequencies, under short-circuit load. With short-circuit load there are no circuit elements external to the tran- sistor to downgrade the performance. Therefore, with Eq. 8.50 as the least possible input capacitance, the short-circuit limit frequency for the transistor is defined as 1 /,= (8.51) 2n(C b . -i C bc )h lt A transistor is operable at frequencies above/, but at values of A,, below h ft0 , as shown in the plot of h f , against///) in Fig. 8.21. The value of/, is used as a frequency figure of merit to compare transistors. With frequency/ well above/,, the value of///", > 1 and the denominator of Eq. 8.49 simplifies to give h, h " ~ m (8.52) The h [t curve at large//, values falls at -20 dB per frequency decade and if the curve is extended to a frequency / = f T , where h ft has fallen to unity or OdB, we have another frequency limit of the transistor, f T . Then from Eq. 8.52 1 = h f'« TWe fr = ffh/t (8.53) The Frequency Limit of the Transistor 187 35 J l 30 S J.J 1 .0 dB/De cade X 20 pa ^ 15 10 h\c-/-: 5 o c-h > % 5 . 1 1 i i i i i i 1 1 ! 0.1 0.2 0.5 10 20 50 f/f. Figure 8.21 High-frequency performance of a transistor. Substituting/, from Eq. 8.51 gives fr = fl /fQ Q I (8.54) 2n(C b . -|- Cjh, t 2n{C b , + C bc ) since g m0 = h t Jh„. The transistor bandwidth is/ z — /, but, for a transistor,/, is at zero fre- quency and fi = /, so that BW =/, (8.55) for the transistor. Equations 8.53 and 8.54 represent a product of gain and bandwidth. This gain-bandwidth product, f T , is dependent only on transistor parameters and is a constant for a given transistor. Values of/, or/ r are given by the manufacturers and both serve as figures of merit, useful in selec- tion of a transistor for a given frequency range. When connected in a practical circuit the frequency limit becomes /, because of the presence of a load R and the Miller-effect capacitance. The first step in selection of a transistor is to determine that it has a needed value of h f , and the second step is to determine that/, is well above the expected highest operating frequency. If f T is given in the transistor specifications, Eq. 8.53 may be used to find/,. We have a similar gain-bandwidth figure of merit for the FET: G-BW=/ r = Sm 2n(C„ 4- C„) and for a triode or pentode vacuum tube: G-BW = ,S >.; 2n(C,„ + C„) (8.56) (8.57) 188 Frequency Response of RC Amplifiers Example: Consider a transistor with/,- rating given as 20 MHz. This gain-bandwidth product tells us that a current gain of 100 is theoretically possible with a bandwidth of 200 kHz or that a current gain of 10 is ob- tainable to a frequency of 2 MHz. Another transistor having f T = 5 MHz would have a possible current gain of 10 to a frequency of only 0.5 MHz. 8.11 The Common-Base Connection at High Frequencies By use of the figures of merit, we can compare the frequency range of a transistor with the emitter common to one with the base common. At mid- frequency we have a mld as the current gain of the common-base configuration and at any frequency a = , a -"' (8.58) The frequency/, is identified as the upper band limit or — 3-dB frequency of the transistor alone, in the short-circuit common-base connection in Fig. 8.22. fl = Figure 8.22 Transistor in the C-B circuit with a short-circuit load. The short circuit is across C tc and eliminates that capacitance from the circuit so that C„ - C b . (8.59) Also "lb — (8.60) 1 + h f . ~ h ft and the input resistance is much less than that of the transistor with emitter common. The reactance of C b , remains large with respect to its shunting resistance to a higher frequency with base common. Using C„ and h lb , we have the limit frequency/, defined as 1 h, /.= — 2a _ g„ (8.61) 2nC,(hJh f ,) 2nCJ, lt 2%C bc Comparison of Eq. 8.61 and 8,52 shows that because of the reduction in Bandwidth of Cascaded Amplifiers 189 input capacitance /. > hfJf ( 8 - 62 > and by reference to Eq. 8.54 /. >/r (8.63) Comparison curves for the current gains of a transistor connected with emitter common and with base common are shown in Fig. 8.2 1 . The common- base connection has a greater gain-bandwidth product than does the con- nection with emitter common. The parameter/, is a figure of merit for a transistor with base common to input and output. 8. 12 Bandwidth of Cascaded Amplifiers The overall high-frequency gain for a number of stages of amplification may be written in decibels as Mhi) Mold) dB - 20 log {l ^ J lhyvll + 20 log n + {f ) fuyvil I 20 log . 1 + [i + (flhcYV n v/hcref lt ,,f 2b ,f2 e , ... arc the limit frequencies of the respective stages. We invert the ratios, use a negative sign, and transfer the square root operation outside the logarithm: |,dB=-.O,og[l + (£) 2 ]-lO.o g [l + (0] -,O,og[, + (0]--. (8.64) A similar expression involving fiJf,fi b /f,fulf, ... can be written for the low-frequency response. The highest/, and the lowest/, frequency would primarily determine the limit frequencies of the complete amplifier. There- fore it does not pay to overdesign the separate stages. Consequently we often use amplifiers of n identical stages in cascade. We would have the gain ratio overall, (8.65) Vi -J- (flfz) for n stages, with/, the same for all stages. We define / 2 ' as the limit frequency of the overall amplifier; that is, at f=fi the overall gain ratio is \\sj~l ' . Then 190 Squaring and taking the reciprocal, Frequency Response of RC Amplifiers 2- =. + (£)* & = V2"" - 1 72 (Hz) (8.67) where/, is the limit frequency of one stage. Similarly we derive an expression for/,', the low-frequency limit for the overall amplifier, as /■' = /, (Hz) (8.68) V2"" - 1 where/, is the limit frequency for one stage. With gains plotted in decibels, the high- and low-frequency asymptotes for the gain curves have slopes of 20ft dB per decade and — 20n dB per de- cade, as shown for the high-frequency region in Fig. 8.23. Table 8.3 and Fig. 8.23 indicate the bandwidth narrowing that occurs as we cascade identical amplifier stages to obtain increased overall gain. For instance, with three stages the low-frequency cutolT or limit frequency is raised by a factor of almost 2 and the upper limit frequency is reduced to almost \. Thus by cascading three stages we have reduced the overall bandwidth to about 50 per cent of that of each stage. TABLE 8.3 Bandwidth Limits for n Identical Stages fufi overall limit frequency A.fi ■ limit frequencies per stage n /;//, n filh 1 i 1 1 2 1.56 2 0.65 3 1.96 3 0.51 4 2.30 4 0.43 5 2.59 5 0.39 To restore bandwidth, it is necessary to overdesign each stage, in this example by doubling its/ 2 frequency and halving its/, frequency. If we have stages with differing values of/ 2 , as/,,/*, . . . , an approximate value for/ 2 ', the overall frequency limit of the amplifier, can be found by I s-WFF Frequency Emphasis and De- Emphasis 191 0.5 I (111 Figure 8.23 Generalized n-stage gain curves. 8. 13 Frequency Emphasis and De-Emphasis The variation of output with frequency obtained with RC circuits is applied in other ways, including audio system tone controls, pre-emphasis and de- emphasis circuits in FM transmitters and receivers, and in tape recording. In such applications the limit frequencies are usually called turnover fre- quencies. The several curves can be drawn by the asymptote techniques of Sec. 8.5 and 8.9. Figure 8.24 shows a circuit for bass boost in an audio amplifier. It operates with a gain of A and the circuit reduces the middle and high frequencies. By 20dB/Decade ■ WW (a) /"(Log Scale) (b) Figure 8.24 Bass-boost circuit. 192 Frequency Response of RC Amplifiers reducing these frequencies the circuit appears to boost the unchanged low frequencies. The attenuation begins at A = 2*(*, + Rz)C (8 ' 69) with/, usually chosen in the neighborhood of 1000 Hz. The transition ends at A = I 2nR,C (8.70) The level of differentiation between low and high frequencies is the insertion loss, obtainable from Table 8.4 as a function of the respective turnover frequencies. The circuit in Fig. 8.25 illustrates a treble-boost circuit, which actually reduces the mid- and low-frequencies by the amount of the insertion loss. The effect appears to boost the level of the high frequencies with respect to the mid- and low-frequency regions. TABLE 8.4 Insertion Loss for Figs. 8.24 and 8.25 hlfx Decibels ftlfi Decibels 2 -6 20 -26 3 -9.5 30 -29.5 4 -12 40 -32 5 -14 50 -34 6 -15.5 60 -35.5 7 -17 70 -37 8 -18 80 -38 9 -19 90 -39 10 -20 100 -40 (a) ALog Scale) (b) Figure 8.25 Treblc-boosl circuit. Frequency Emphasis and De-Emphasis 193 The treble-boost insertion loss is found from Table 8.4 when the turnover frequencies are chosen as In R,R 2 (8.71) h = + R, litR.C (8.72) By using a variable resistor for R 2 of the bass-boost circuit, the value of /, can be continuously varied. The insertion loss varies and the bass boost appears to be changed. Similar action is obtained in the treble-boost circuit by variation of resistor /?,. In frequency modulation radio systems, the high frequencies of the signal are prc-emphasized by the circuit in Fig. 8.26(a), giving a result that is the inverse of the curve in Fig. 8.26(c). The values of R and Care determined from the time constant RC = 75 x 10" 6 s, resulting in a turnover frequency /, = \/RC = 1/(75 x 10") = 2123 Hz. At the receiver the de-emphasis circuit of Fig. 8.26(b) is used with the same turnover frequency, giving a fall at high frequencies as in Fig. 8.26(c). All signal frequencies above the turn- over are dropped by the amount of the pre-emphasis and their original level is restored; however, the noise frequencies originating in the transmission path and in the receiver are reduced by the amounts of the curve in Fig. 8.26(c). The signal comes out at its original level, while the noise is reduced in level. In tape recording the high frequencies do not record well and accordingly they are boosted in recording. At the playback the high frequencies are re- duced to normal using a circuit with the elements in Fig. 8.24. The resulting reproducer curve is drawn in Fig. 8.27. (a) I VWV- R r± K, dB S 10 15 -20 25 - 3dB- _5&i i/"=2i: 3 Hz N. i i<>i i ' i i 1 1 0.1 0.2 (b) 0.5 1 .0 2 /(kHz) (c) 10 20 Figure 8.26 (a) Transmitter pre-emphasis circuit, RC = 75 x 10"* s; (b) FM receiver dc-emphasis circuit; (c) dc-emphasis of the high frequencies at the receiver. 194 Frequency Response of RC Amplifiers /|=S )Hz -/2 = 1326 Hz i i . i.i .i.i. '■■ 40 35 30 25 3 20 15 10 5 0.02 0.05 0.1 0.2 0.5 1 2 /(kHz) Figure 8.27 Standard tape playback curve, 3.75 ips (9.5 cm/s). 8.14 Review The frequency range covered by an /?C-coupled amplifier may be divided into three parts: the low-frequency region, the high-frequency region, and the frequencies between, called the mid-frequency region. In the last region, all reactances in the circuit arc negligible and the gain is constant with frequency. We use this region as a gain reference, or dB. If the gain is not constant across all signal frequencies, then we have an amplifier with frequency dis- tortion. In the low-frequency region the gain is affected by the scries blocking capacitor and the gain starts at a low value, rising at 20 dB per decade up to /, at which the gain is —3 dB. The frequency/, is determined by the blocking capacitance C c and the series value of the load It and h lr of the following transistor. The high-frequency region is bounded by a limit frequency f 2 at — 3 dB from the mid-frequency gain level; above/ 2 the gain falls, ultimately reaching a rate of — 20 dB per decade. The frequency / 2 is inversely proportional to C,„ the Miller capacitance, and to the parallel value of R and h lt . Each type of device has its own ultimate figure of merit as the gain-band- width product. This is a frequency at which the gain is unity, or OdB, and comparison of frequency performance is possible by using the G-BW figures of the devices. Review Questions 196 REVIEW QUESTIONS 8.1 Why do we need to consider the frequency response of an amplifier? 8.2 Define frequency distortion. 8.3 Why are we able to consider the three frequency regions separately? 8.4 What type of distortion is often present in RC amplifiers? 8.5 For a rectangular 1 -fis pulse, repeated 60 times per second, there are harmonics every 60 Hz. How many harmonics must be reproduced by an amplifier for perfect reproduction of the pulse? For an approximate reproduction? 8.6 What function does the blocking capacitor serve? 8.7 The scries reactive clement determines what frequency limit? What frequency limit is fixed by the shunt reactances? 8.8 What function does /?, and Ri serve in a transistor amplifier? 8.9 What function does R c in an FET amplifier, and R„ in a vacuum-tube ampli- fier, serve? 8.10 Draw the small-signal high-frequency model of an FET and label the elements. 8.11 What is the effect if the emitter resistor R E is not bypassed? 8.12 How would you choose the capacitance value of a blocking capacitor? 8.13 What frequencies bound the mid-frequency region ? 8.14 What factors determine/, for the low-frequency range? 8.15 What factors determine / 2 for the high-frequency range? 8.16 A transistor amplifier has/, 150 Hz; what is the gain at 300 Hz, with mid- frequency as the reference gain? 8.17 A transistor has //„ - 800 £2; what maximum reactance may C c have in a well-designed amplifier at the lowest frequency used? 8.18 In Question 8.17, why are we interested in the reactance of C c at the lowest frequency? 8.19 An amplifier has a mid-frequency gain of 37 dB; its/, value is 15,000 Hz. What is the gain in decibels at a frequency of 45,000 Hz? 8.20 What is the physical origin of the two internal capacitances in the high- frequency model of the junction transistor? 8.21 Repeat Question 8.20 for the FET. 8.22 Repeat Question 8.20 for the triode lube. 8.23 What is the Miller effect? 8.24 Is it a capacitance or a gain that is responsible for the Miller effect? 8.25 Why do we use the short-circuit load to find the frequency limit of a transistor? 8.26 Define/,; define/-; what is the relationship between/, and/-? 8.27 Why does h, t of a transistor decrease at high frequencies? 196 Frequency Response of RC Amplifiers 8.28 How should / 2 of an amplifier be related tof T of ihe transistor? 8.29 Show that variation or R, in Fig. 8.25 will vary the high-frequency boost of an amplifier with a tone control. 8.30 Why is a de-emphasis circuit used in an FM radio receiver? PROBLEMS 8.1 In the circuit of Fig. 8.28(a) with transistors having /;„ = 2000 SI and h f , = 40, find the value of C that will reduce the gain at 100 Hz by 3 dB below the mid-range region. 8.2 An rtC-couplcd amplifier with a single stage has /", - 82 Hz,/ 2 = 12,500 Hz. Sketch the complete frequency-response curve, using a log scale on the fre- quency axis and gain in decibels. 8.3 In the circuit of Fig. 8.28(b) the transistors have g„ = 0.015 mho and //„ = 900 SI. What is the decibel mid-frequency gain from port 1,1 to port 2,2? What is/,? 5 kft < I Mfi r€> Figure 8.28 8.4 An FET with g m - 0.004 mho is used in the circuit of Fig. 8.29(a), with C„ = 2 pF and C, d m 4 pF. What are the upper and lower half-power frequencies? What /, will produce 10 V at V in the mid-frequency range? 8.5 A triode amplifier has C c - 0.005 fiF, R, = 0.25 MSI, r p = 27,700 £2, g m - 0.0026 mho, and /? =- 0.10 MSI. Find A v{mU) ; also find A, at 100 Hz. What is /,? 8.6 Using a transistor with h, e = 850 SI, h fc = 60, R = 5000 £2, C h , = 100 pF, and C bc = 3 pF, what is the transistor input capacitance? 8.7 The transistors in the amplifier of Fig. 8.29(b) have h u = 1600 fi, h f , = 40, C be = 4 pF, and C„, = 100 pF. (a) Find/", and/ 2 for the amplifier. (b) What is the mid-frequency gain ? M Problems 197 lOkft Hf- 4.7 kfi • 5.6 k« (a) (b) Figure 8.29 8.8 A transistor (2, in the circuit of Fig. 8.30(a) has h„ = 1200 SI, g m - 0.005 mho, and C = 0.05 (iF. Find /, and the gain at 30 Hz. 8.9 The triode of Fig. 8.30(b) has r, 1 2,000 Q, g m = 2500 //mhos, C, k = 3 pF, and C pk = 3 pF. Find the bandwidth in hertz for the gain between ports 1,1 and 2,2, with R = 40,000 Q for T x . 60 kfl (a) (b) Figure 8.30 8.10 Given the following transistor measurements at low frequency: //„ = 600 Si C bc = 3 pF A /r = 30 C bt = 100pF Find ff,f T , for the transistor. 8.11 When the transistor of Problem 8.10 is used in the C-E amplifier of Fig. 8.30(a), find/ 2 . Also find the decibel gain at/= 2.5/i. 8.12 Plot the high-frequency gain in decibels for Problem 8.1 1. Prove that your gain figure is correct at 2.5/ 2 . 8.13 An amplifier has three identical stages with each having/, - 10 Hz and f 2 = 25 kHz. What are the limit frequencies of the amplifier? 198 Frequency Response of RC Amplifiers 8.14 Wilh V 80, C 6c = I pF, C*. = 75 pF, and /,„ . 600 £2, find f„ and f T or the transistor. What gain is possible with BW = 100 MHz? 8.15 Specify the/, and/, design frequencies for each stage of a four-identical-slage amplifier if the overall bandwidth required is from 100 to 450,000 Hz. 8.16 Show that a rate of fall of 20 dB per decade is equivalent to 6 dB per octave (double frequency). 8.17 You wish the gain to fall at a rate of —60 dB per decade at a frequency that is high with respect to your operating frequency. How will you design your amplifier? 8.18 An amplifier has/, = 80 Hz. Sketch the frequency-response curve on a log frequency scale from 10 to 500 Hz. What is the rate of gain fall at 0.1 Hz? Use a decibel gain scale. 8.19 A transistor has/, = 10 MHz and h fco - 100 at a mid-frequency. Find It,, at 15 MHz. 8.20 A transistor has/ r = 250 MHz and h fco - 64. Find h f < at 5.0 MHz. 8.21 An amplifier has three nonidentical stages with gains of A t = 18 dB, A 2 *» 20 dB, and A 3 = 14 dB at mid-frequency. What is the overall gain, expressed as An = VJV,1 8.22 A two-nonidcntical stage amplifier has a first stage /, ^ 40 Hz and a second stage/, -= 15 Hz. Find/, for the overall amplifier. 8.23 Plot the high-frequency region gain on a log frequency scale for a six-stage amplifier, with/ 2 = 1 MHz for each stage. Use a decibel gain scale. 8.24 The G-BW product for a transistor is 120 MHz. With mid-frequency g m0 = 0.010 mho and R - 2000 Q for the load, /;„ = 2200 fi. Determine the gain to be expected at a band limit of 4.5 MHz. 8.25 A given amplifier has an/ 2 value of 30 kHz. At what frequency is the amplifier gain down only 0.1 dB from its mid-range value? 8.26 For the amplifier of Problem 8.24, we find the gain is 1.5 dB below the mid- range gain. What is the frequency? 8.27 A transistor has a mid-range a - 0.97 and/ = 0.55 MHz. Find the magni- tude of a at 0.75 MHz. 8.28 A one-stage amplifier has A. = 30 and / 2 - 400 kHz. The /, value is to be increased to 600 kHz. What change can you make in the amplifier? What will the new A v become? 8.29 An amplifier for an electronic voltmeter must have A, constant within 5 per cent up to 100,000 Hz. What/, value must the amplifier have? If composed of three identical stages, what/ 2 value must be specified for each stage? 9 Negative Feedback in Amplifiers In electronic circuit design we are often forced to sacrifice performance in one area to achieve better performance elsewhere; this is called a trade-off. In the use of negative feedback, we build extra gain into the original design and trade off this excess gain to obtain reduced distortion, stable gain, greater band- width, and changed amplifier input and output resistances. When we use solid-slate devices and integrated circuits, we find that the price paid for the additional gain is relatively low. Negative feedback makes our amplifiers nearly precise and ideal. 9. 1 The Black Box with Feedback Negative feedback is an old and fundamental process, used in many fields to make the output response of a system more nearly correspond to the input signal. We compare the output with the input and utilize any difference as a corrective signal. The principle is apparent in such a simple activity as placing a pen on paper; without optical feedback of the difference between actual (output) and desired (input) locations of the pen, we could not write. The children's game of "pin the tail on the donkey" is another example of our inability to perform as usual without feedback in some form. In electronic amplifier feedback we compare a sample of the output wave- form against the input waveform. Any difference between the two signals gives an error voltage that is applied to the amplifier so as to change the output 199 200 Negative Feedback in Amplifiers waveform and reduce the difference toward zero. Thus we force the output toward equality with the input and somewhat unprecise amplifiers become almost ideal gain elements that give an output like the input. The C-E amplifier in Fig. 9.1 has negative feedback applied through resis- tor R f and the blocking capacitor C f . A portion of V„ is transmitted back to the input circuit through R,. Because of the 180" phase inversion in the C-E amplifier, the voltage fed back as V f is opposite in phase or negative to V ( and the feedback voltage is compared with and subtracted from the input voltage. The difference becomes the amplifier input. Network Figure 9.1 A practical feedback amplifier. Figure 9.2 shows an amplifier system of gain (9.1) A V. from port 1 to port 3. The internal gain of the black box from port 2 to port 3 is K -4 = v\ (9.2) The output is sampled by the /? network and the result V, is subtracted from the input at the mixing point £ (sigma), as shown by the indicated polarities. P ■* -±K Figure 9.2 Feedback applied to a black box amplifier. The Black Box with Feedback We have 201 (9.4) A K Vf - PK where /? is less than unity and the /? circuit is designed to produce zero phase shift in the operating frequency range. A resistance voltage divider serves well, as the R r , R b divider in Fig. 9.1. At the amplifier input, V, = V, - V, - V, - fiV (9.3) From Eq. 9.2 we have A V, =» V\ and substitution of Eq. 9.3 gives A(V, - pV e ) = V K;,(l -I Afi) - AV, We find the gain from port 1 to port 3 of the feedback system by use of Eq. 9.1 as This is the fundamental equation of feedback, expressing the closed-loop gain A' as dependent on the internal gain A and on the feedback factor /?. In Eq. 9.3 the feedback voltage V f is presented to the input circuit in sub- tractive fashion. The denominator 1 1 + Afi\ > 1, and the feedback is nega- tive. Equation 9.5 then shows that | A' | < | A | and the gain of the system with feedback is less than the internal amplifier gain. Thus gain is sacrificed with negative feedback. If A is negative, as is usual in C-E amplifiers, we reverse V f from the /? network, resulting in a positive A/} term in Eq. 9.5 and so retain the negative feedback. If the phase of V f reverses, as may happen with nonresistive /? networks, the feedback voltage V f becomes additive to V, in Eq. 9.3 and the denomina- tor of Eq. 9.5 shows that 1 1 -\- Afl\< 1 and the feedback is positive. The closed-loop gain is | A' \ > \A\ and the gain of the feedback system is greater than the internal gain. This is a condition of gain instability since it includes the case at Afi = — 1 where the gain becomes infinite. The amplifier then becomes a generator of signals and when such action is wanted, we call the circuit an oscillator; these circuits will be studied in Chapter 13. The condi- tion of positive feedback is avoided in amplifiers. A measure of the amount of negative feedback introduced into an ampli- fier is given by the gain change in decibels as dB of feedback = 20 log -J (9.6) The latter expression can be translated into another that is useful. Look at ? = ^j— = 1+j4/? (9.7) 202 Negative Feedback in Amplifiers so that the decibels of feedback can also be written as dB of feedback = 20 log (1 |- A0) (9.8) Because of the reduction of system gain by feedback, the input at port I, 1 must be greater than the amplifier input at port 2, 2. By our definitions y. - A'V, V'o - AV\ From these relations, for equal output P.-yFj - £— K - (1 + Afi)V', (9.9) 1 +AP The system input must be (1 I Ap) greater than the amplifier input at port 2,2. Example: An amplifier has a gain A = 70 and a normal input signal of 0. 1 V. Feedback with /? — 0. 1 is added, giving Ap = 7.0. The closed-loop gain is it A 70 _ one A "1 -V Ap~ 1 H-7.0~ 5 '° An input voltage K, = (1 f ^)K; = (1 + 7) x 0.1 = 0.8 V will be needed. The output voltage of the amplifier is V. = A'V, = 8.75 X 0.8 = 7.0 V or V' 9 = AV, = lQx 0.1 =7.0V These relations apply to the system and to the internal amplifier, at ports 1, 1 and 2, 2, respectively. With feedback the amplifier input voltage is K ' :? - 70 ~° l V The external signal requirement is raised from 0.1 to 0.8 V by the addition of negative feedback, but inside the loop the amplifier is operating with an input of 0.1 V and an output of 7.0 V, with or without feedback. 9.2 Stabilization of Gain by Negative Feedback When amplifiers are used in calibrated electronic instruments, such as volt- meters, internal gain changes will affect the instrument accuracy. Changes can be expected, due to supply voltage shifts, aging, and particularly operating Stabilization of Gain by Negative Feedback 203 temperature. Negative feedback is used to make the amplifier gain indepen- dent of these variables. For a percentage change in A, AA/A, we find a resultant percentage change in the system gain as AA'/A'. That is, Thus the feedback gain change is much less than the change in the internal amplifier gain. To reduce the sensitivity to internal gain change still further, we can make AP very large so that Eq. 9.5 reduces to 1 A'S P (9.11) With Ap ^> 1, we no longer are concerned with maintenance of an exact value of A because the overall system gain is dependent only on the elements of the p network. When constructed of precision resistors, a precise gain is retained over long periods of time. The price paid for this stability, of course, is a reduction in feedback system gain. Example: A range of ± 10 per cent is allowed for the internal gain of an amplifier, with A = 100. How can this gain change be reduced to ± 1 per cent? What is the resultant gain? We have AA/A = 0.10 and desire AA'/A' to be 0.01. Then 1 0.01 - X0.I0 1 +Aft 1 + A0 = 1Q Since A = 100, 100^ _I0—I=9 /? = 0.09 We then have Ap = 9 for the feedback system. With 1 I AP = 10, the feedback system gain is .,_ A 100 _. , and we have reduced the gain by a factor of 10 in stabilizing the gain by a factor of 10. If we design our amplifier for a gain of 1000 ± 10 per cent, however, we have I and with A = 1000 001 -TTAt I + AP = 10 x 0.10 1000;? = 9 P = 0.009 204 Negative Feedback in Amplifiers and we have Afi = 9 again. But the feedback system gain is now 1000 A' 1 +9 - 100 This is the desired gain but it is now stabilized to — 1 per cent. We have had to buy an amplifier with a gain of 1000 to obtain 1 per cent stability at a gain of 100. This, in certain applications, may be a small price to pay. Example: An amplifier is designed with A = 4000. Choosing /? = 0.04, we have Then A' = 40 = 4000 x 0.04 = 160 A 4000 = 24.84 1 + Afi ~~ 1 + 160 Suppose the internal gain doubles to 8000. Then A0 = 8000 x 0.04 = 320 8000 A' = = 24.92 1 + 320 Gain A might drop to 2000, in which case Aft = 2000 X 0.04 = 80 a ' = ttto- 24 - 69 We have demonstrated that with A large, Eq. 9.1 1 holds and the gain can be maintained close to A'- 1 - ' -25 regardless of large variations of the internal amplifier gain A. 9.3 Bandwidth Improvement with Negative Feedback In Chapter 8 we showed that the high-frequency gain of an /?C-coupled amplifier was A "r(mld) (9.12) Bandwidth Improvement with Negative Feedback 205 Using a resistive fi network, the phase angle of /} can be held constant over the frequency band. For a feedback system, we could write A, [mldl ,>_ a,™ ._, i + um) = ^rlroli [i+Mo-d+g (9.13) We learned that we are at a limit frequency when the terms in the denominator are equal so -& - 1 + M«-id» and our upper limit frequency with feedback, designated f\, is n = [l + Mewl/. (9.M) The upper frequency limit of the system has been raised by (1 — Af}). Similarly, we can show '»-l+Mw« (9 ' I5) and the low-frequency limit is reduced by feedback. The bandwidth has been materially increased. Using f 2 as the bandwidth or assuming /' 2 > /',, the gain-bandwidth product with feedback is G-BW - , .-V 1 ' I' + fr*'«-«d/a = ^.w/ - . ( 9 -l 6 ) and the G-BW figure is seen to be independent of the feedback p. The curves in Fig. 9.3 illustrate this, being reduced in gain as the frequency band widens. It is apparent that we have traded gain for bandwidth. Physically large and expensive blocking capacitors can often be avoided when the mid-frequency bandwidth is expanded to lower frequencies, by use of negative feedback. Gain MB) A Figure 9.3 Effect of negative feedback on bandwidth. 206 Negative Feedback in Amplifiers 9.4 Reduction of Nonlinear Distortion Large-signal amplifiers, forced 10 operate in wide excursions across the device volt-ampere characteristics, will generate harmonics in the output signal. Negative feedback reduces such internally generated distortion of the the waveform. With the feedback loop open in Fig. 9.4, we have r a -AV',+ V k (9.17) where V h is the generator representing the internally generated distortion waveform. ~© V! v: (9.19) Figure 9.4 Distortion inside the feedback loop. If we add negative feedback, the input signal is V\ r-V.-Vr (9.18) and the output signal is V, - AV\ + V h Substituting V = A<V,- V f )+V h and using Eq. 9.9 for V, with feedback, as well as V, = ftV'„ we have V' -A[(l ! Aft)V, - ftV B ] + V h Sorting the terms, we have v ;(i + Aft) = ,4(1 + ap)v; + v„ Making outputs equal, or V = V'„ we compare Eq. 9.17 without feedback and Eq. 9.20 with feedback. We see that the use of negative feedback has reduced the harmonic distortion by the factor 1/(1 + Aft), or D (9.20) Z>' = (9.21) i + Afi where D' and D represent per cent distortion. This result is of great importance in the design of high-power audio amplifiers. But with large Aft values the bandwidth is increased also and the Control of Amplifier Output and Input Resistances 207 high-frequency limit of audio amplifiers is frequently raised above 100 kHz. This occurs even though audio signals present no components over 20 kHz. Should Aft shift in phase angle in this extreme frequency range, there may be positive feedback and gain instability can be created. Example: An audio amplifier of 500 voltage gain produces 1 1 per cent harmonic distortion at full output. It was designed, considering C„ of the transistors, to yield an upper frequency limit of 8 kHz. Tolerable distortion is considered to be 1 per cent. What value of ft is needed to reduce the distortion and what is the bandwidth extension? From the distortion relation D ~Tft D' = 0.01 = 1 + 0.11 1 + Aft \-r Aft=\\ and A ft = 10. With A = 500 we have The/j limit of the amplifier is extended by (1 - Aft) = 11 so that the/i limit with feedback is 1 1 x 8 kHz »■ 88 kHz. To improve the distortion situation, it is seen that we have extended the frequency range far beyond the needs of the audio signal. 9.5 Control of Amplifier Output and Input Resistances For a constant input signal, the feeding back of a voltage sample V f , pro- portional to the output voltage of an amplifier, tends to maintain the output voltage at a constant value. This is done in Fig. 9.5(a) and constitutes voltage feedback. The amplifier appears to have a low output resistance. Similarly, the feedback of a voltage V f proportional to the load current tends to control the load current at a constant magnitude, independent of load resistance. This is the property of the circuit in Fig. 9.5(b) and represents current feedback. The amplifier appears to have a high output resistance. It is often desired to alter amplifier output resistances so as to supply a needed output current easily or to power match a load such as a loudspeaker. The two methods of obtaining feedback voltage provide the circuit designer with means for lowering or raising the output resistance of an amplifier. Considering voltage feedback first, as in Fig. 9.5(a), the output resistance R'o may be found by short-circuiting the independent signal source V,. Then 208 Amplifier Negative Feedback in Amplifiers Amplifier (a) (b) Figure 9.5 (a) Voltage feedback, scries input ; (b) current feedback, scries input. we apply a voltage V T at the output and R = V T jI T . With a short at V„ the input is V, = — RV T with the negative sign as a result of the subtraction of V f . From the currents in Jt„ and it follows that •H=4^'0«- R' = LZ — ■» ° It II- A,.B (9.22) The output resistance of the amplifier is reduced by the introduction of negative voltage feedback. Referring to the current feedback circuit in Fig 9.5(b), we short V, and have V, = R f I T . Then V T . (A„R f i R | R f )l T With the feedback factor being we have Since R r < R B - Bj. P Rf + R* (9.23) (9.24) K '-G^ftc +I )^ +J ^ /f:=7 2: =/? (i i /*,/?) •T (9.25) (9.26) which shows that the output resistance increases by use of negative current feedback. The manner in which the feedback voltage is introduced into the input circuit can alter the input resistance of an amplifier. With the feedback volt- A Current Series-Feedback Circuit 209 age V f introduced in series, shown in Fig. 9.5, the input resistance with feed- back is R', = *,(1 + A,P) (9.27) and increases with B- When V f is introduced in shunt as in Fig. 9.6, the input resistance is re- duced as (9.28) R ' ~ 1 I A.P The circuit designer can choose /? and the method by which he derives the voltage V f to adjust the output resistance to a desired value. He can choose B and the method by which V f is inserted in the input circuit to alter the input resistance of the amplifier. These results are tabulated in Table 9.1. & \ niplifier ~- — n + *'i |*<~> | + K Figure 9.6 Shunt input of the feedback voltage. TABLE 9.1 Effect of Feedback on Amplifier Resistances Voltage derived : Current derived : Series input: Shunt input: R a decreases R increases Ri increases Ri decreases 9.6 A Current Series-Feedback Circuit In Fig. 9.7(a) the unbypasscd emitter resistor R K provides a feedback pro- portional to load current; therefore it is current feedback. The voltage across R E is Vf and this is introduced in series with the input signal so that we have a current-series feedback circuit. That is, V„. = V,-V f (9.29) From the equivalent circuit V, ^ V bt + Vf = h,M •■ (/.-I •/,)** - [*,. + (1 + h f ,)R E ]h (9-30) 210 Negative Feedback in Amplifiers (a) <b) Figure 9.7 (a) Current feedback, series input; (b) equivalent circuit. Since V„ — — RI C = —h f ,Rl b , the gain can be obtained by use of Eq. 9.30 as K -h,,R A„< mii) y'-i^Q \h f .)R E By dividing out the h„ term and neglecting l < h f „ we have A,tnM\ = -g„R (9.31) (9.32) It is of interest to find that the feedback theory previously developed does apply to this practical circuit. The feedback factor is B = voltage feedback = (I + h, c ) R B / b ~ _Re p load voltage ~h f ,Rl b R Without feedback (R E = 0), the gain of the amplifier is A = -g m R We showed that with feedback the gain is r- A Using Eq. 9.33 and 9.34 we can form the feedback gain: -gmR -g m R (9.33) (9.34) A' = I+(-fc*>(-£) **■* (9.35) which is Eq. 9.32 written from the feedback equation. The negative sign on /? A Current Series-Feedback Circuit 211 appears because A v is negative for the one-stage C-E amplifier; this situation was previously discussed. Thus our feedback theory is confirmed. The input resistance can be obtained directly from Eq. 9.30 as VJI b , where « ( -5 I -*. + (i + h,.)R B = h„ + h f ,R E = A„(1 + g m R e ) (9.36) The series input of the feedback voltage has raised the input resistance from the /»„ value, present without feedback. Our theory says /?;-*,(' I Afi) (9.37) The input resistance is h u with no feedback (R B = in Eq. 9.36). Using the A and fi relations, K = /',.[l * <-*-*)(-if )] - A,.(l + g m R K ) (9.38) which is Eq. 9.36 derived from the circuit. To obtain the output resistance, we shall merely use Eq. 9.26: 1 + A0 R' = R since R is the output resistance at the 2, 2 port with no feedback. Using our A and /? relations, /?;-/?[l-f(-g m /?)(-^)] - *(1 + g m R B ) (9.39) with feedback. This is increased by reason of the current feedback. Example: For the circuit in Fig. 9.7, we use R E = 1.5 k£2, R = 10 kQ, h„ = 2 kSl, h f , — 50 and h ar — 10~* mho. Find the gain and input and out- put resistances, without and with feedback. We have gm _/'/.__ 50 2(KH) = 0.025 mho Without feedback, A = -g n R - -25 X 10" 3 X 10 X 10' = -250 R t = h„ = 2000 Q /?„ = /?= 10,000 Q (Mh ot neglected) With feedback. r_ -g m R _ -250 1 +g m R B ~ 1 t (25 x 10-* x 1.5 x 10') = -6.5 212 Negative Feedback in Amplifiers To confirm the gain, we calculate 8 as '— ¥- 1 500 10,000 and using the feedback gain expression A -250 = —0.15 A' = = -6.5 1 + AB ~ 1 + (-250K-0.15) K = h,.(\ + g m R E ) = 2000(1 | 25 X 10" 3 x 1.5 x I0 J ) = 77,000 fi R' B = ' '.^ - 10 4 (1 + 25 X 10-' X 1.5 x 10 3 ) = 380,000 n 5. 7 Voltage-Shunt Feedback Circuit The circuit in Fig. 9.8 gives shunt input for the voltage-derived feedback; therefore it is a voltage-shunt feedback circuit. A current summation at the base yields £ + // - h and we can write /, v. - r* R. K-t\.~y. R. l(MAAAr (9.40) (9.41) (9.42) lo- t-o2 -02 lo- ^O *i s £ -02 Voltage Feedback with the FET 213 In writing Eq. 9.40 and 9.4I we have assumed that the internal gain A is large and V bf is therefore small. Likewise, in using /, = —VJR in Eq. 9.42, we have said that 7, < I c or that R, > R- Summing the currents, V. ■ V. _ Vq R, r R f h fc R V °\h fc R R f ) R, Then V„ I / I V=~R,[ 1,1 (9-44) (9.43) (a) (b) Figure 9.8 (a) Voltage feedback, shunl input; (b) equivalent circuit. and the gain is y* ' / ' \ y.~ *J_l + -L , _ V B R, h,.R A V, ~ R,R f -\h tc R Forhf.R » R„ the gain is determined solely by the feedback resistors R f and R„ as A'2Z-& (9.45) giving a very stable gain. This is equivalent to the result of Eq. 9. 1 1 and so we see that B- -£■ (9-46) for the shunt-feedback circuit. The result of Eq. 9.45 will be further discussed in Chapter 10. 9.8 Voltage Feedback with the FET In the FET amplifier in Fig. 9.9, a portion of the output voltage is provided by the R„ /? 2 voltage divider and inserted in series with the input. A similar circuit is useful with the vacuum lube. This is a voltage-series feedback ap- plication. By opening R, the feedback is removed from the circuit and the gain is A, -g m R D (9.47) The sum R, + R z is made large with respect to R„ so that /, -C h- The current in the voltage divider is V. A = R, +R 2 and the voltage feedback V f is R, + Ri (9.48) 214 Negative Feedback in Amplifiers The Emitter Follower as a Feedback Amplifier The gain with feedback is A' = 215 r4 f ' ' IO- + Figure 9.9 An FET with voltage-scries feedback. This feedback signal is introduced as r,- K- V, (9.49) and the feedback is negative. The feedback factor can be obtained as (9.50) B =^-t = ~ R * This is an accurate result because there is no gate current to consider. The gain with negative feedback is then A' = TTAp -z»R D ~gn,R D 1 + *. Ri I Ri (9.51) Example: An FET amplifier has g„ = 0.004 mho, R D - 10,000 CI, Ri + Ri = 100 kQ, and /? = -0. 10. Find the gain with and without feedback. Without feedback, A, = -g m R D = -4 X 10' J X 10 4 = -40 The feedback resistor R 2 is found from B = ^i P Ri+R* R, = -0(R l -I- R 2 ) = 0.10 X 10 s = 10* Q ' ~g-*» - 40 , H gm RoRi '7ZIZ in-J 10< x 1Q4 '*. + R* 1 + 4 x 10- W -40 5 Using Eq. 9.5 as a check, 40 A '' 1 H AB ~ 1 + (-40X-0.10) = -8 3.9 The Emitter Follower as a Feedback Amplifier From the emitter follower circuit in Fig. 9.10, we have V bc =V,-V which is equivalent to V\ = V, - V, (9.52) for our general feedback amplifier. The result of Eq. 9.52 tells us that V t = V„ and the entire output voltage is being fed back to the input. This means that (9.53) >-£-&-' Since the output voltage is being fed back, the circuit gives voltage feedback with B = 1 and is extremely stable. Vcc ? I o 1(- Vs R } |o- -\^>2 'v >'„f g„,K,(t) I c- 'fr + M t'. -o2 + -o2 (a) (b) Figure 9.10 The emitter follower. 216 Negative Feedback in Amplifiers Writing and V. = (h + I C )R E S h f< R E I b V, = h„l b + h f .R B l„ = (/.„ + A,,* e )/ 4 we find the gain as 4.~,-& A /f /?, gm* £ ~~ S I (9.54) ' h lt i /; /r fl E l + gm R E which is the result obtained for the C-C circuit. The input resistance is in- creased by the series feedback and the output resistance is reduced to «= \/g n , as for the C-C circuit, which the emitter follower is. Similar results are obtained for the FET source follower and the triode cathode follower. 9. 10 Multiple-Stage Feedback When we cascade C-E amplifiers, each stage adds a phase shift of 180°,' or n x 1 80" is the phase shift for /; stages. The polarity of the V, voltage must be maintained negative to V, for negative feedback and AR must be positive, cither as a result of ( i A)(+R) or (-A)(-R). With a single stage of C-E amplification, the output V is at 180" to the input signal and voltage feedback V, is introduced into the base, where it is negative to the signal as required. This is the method in Fig. 9.8. Because of the 360° phase shift of V with respect to V, in the two-stage C-E circuit of Fig. 9. 1 1 , the voltage feedback V, must be introduced into the emitter. This amounts to reversal of the V, voltage and gives ( \-A)(+fi) = AR. Thus we have methods for insertion of the feedback voltage with n odd or even. Figure 9.11 Voltage feedback, scries input, over two stages. Amplifier Cain Stability with Feedback 217 In combining C-E, C-B, or C-C stages or FET or tube equivalents inside the feedback loop, we must determine if the overall phase shift is an odd or even multiple of 180°. The proper entry point for the feedback voltage V t is then known. Feedback over multiple stages gives a larger value of A, resulting in a larger AR term; therefore, we can have greater reduction of distortion. There is some risk in amplifier stability because with increased numbers of capacitors inside the feedback loop, the phase angle of A may not be exactly 180n° at all frequencies in the response range. Conditions for positive feedback may be approached at the limits of frequency response, resulting in amplifier insta- bility. The major feedback in Fig. 9.1 1 is voltage derived but a small amount of current feedback is added in each stage by the unbypassed emitter resistors. Feedback of both types is additive in an amplifier and the effective R is the sum of the voltage and current feedback R values. Figure 9.12 shows a two-stage C-E current feedback amplifier. With a 360° phase shift, the current supplied from R E opposes the signal current in R, so that the feedback is negative or subtractive to the input signal. Figure 9.12 Current-shunt negative feedback. 9.11 Amplifier Gain Stability with Feedback We have used ideal feedback conditions as they occur in the mid-frequency range of an amplifier, requiring the feedback voltage V, to be opposite or at 180° to the input signal voltage. We can design amplifiers to meet this condi- tion satisfactorily over a specified frequency range. We also encounter situations, however, in which the required phase angle is not present at extremely high or low frequencies, at which the angle of A, approaches 90/i° in RC amplifiers of n stages. At frequencies above f t , or 218 Negative Feedback in Amplifiers below/,, the voltage V t may not directly subtract from V„ and V\ increases. As a result the amplifier output is larger and the gain increases at frequency extremes, as shown in Fig. 9.13, and we have the condition of positive feed- back known as regeneration. ('■am 4» Mid-Range / Figure 9.13 A feedback amplifier gain curve wilh regeneration at high and low frequencies. The dividing line between negative feedback and positive feedback ap- pears at \l + Afi\=l (9.55) and with \l+A0\<\ (9.56) the gain is unstable as a result of positive feedback. When the Afi value leads to \l + Afi\ = (9.57) or Afi — —I, the gain A' becomes infinite according to A A A' = 1 + Afi and this is the extreme condition of gain instability known as oscillation. Using Afi as a stability criterion, we can write Stability: \Afi\>0 Instability: > \Afi\ > -I Oscillation: Afi =- -1 A Nyqujst plot may be used to study the action of Afi and is a polar plot of Afi at all frequencies from zero to infinity. Table 9.2 shows Afi magnitudes and phase angles for an RC amplifier, for A — 40, fi = 0. 1 in Eqs. 8.27, 8.28, 8.47, 8.48. Values from the table are plotted in Fig. 9.14. The frequency point moves clockwise around the plot; at 6 = +45° we have fi, at = —45° we have/ 2 . The mid-frequency range appears on the x axis at Afi — 4.0, since the phase angle is zero in the mid-range. Since Afi never becomes less than 0, the one-stage RC amplifier is unconditionally stable. Suppose that two such stages are used in cascade. At the frequency extremes the amplifier phase angles approach _L180°, and the Nyquist plot Amplifier Gain Stability with Feedback 219 y / 3^ \/ i, i ii , -1 ^^\° \ ' IICj-KJ f 2 X Figure 9.14 The Nyquisl plot. TABLE 9.2 A$ Plot of RC Amplifier m Ap 8 (degrees) flh AP (degrees) +90 Mid-range 4.0 0.1 0.4 84 0.1 = 4.0 -6 0.25 1.0 76 0.25 3.9 -14 0.5 1.8 63 0.5 3.6 -27 1.0 2.8 45 1.0 2.8 -45 2.0 3.6 27 2.0 1.8 -63 4.0 3.9 14 4.0 1.0 -76 Mid-range 4.0 00 -90 swings into the negative amplitude region. It may approach or surround the critical point at Afi — — 1. Such situations are shown in Fig. 9.15. The Nyquist criterion states an amplifier is unstable if the Nyquist curve encircles the — 1 point and is stable otherwise. Mid-Range Figure 9.15 (a) Nyquist plot for a regenerative amplifier; (b) an unstable amplifier. 220 Negative Feedback in Amplifiers By this rule we sec that the amplifier response diagrammed in Fig. 9.15(b) is unstable and will oscillate; that in Fig. 9.15(a) is regenerative due to the near approach to the — 1 point. For this amplifier the gain-frequency curve will have a high-frequency hump. In general, instability can be corrected by change of the Ap phase angle with a parallel R, C circuit in the line supplying V f to the input; or by reduc- tion of A through use of a series R, C circuit across a load, thus reducing gain at f 2 and above. 9. 12 Gain and Phase Margin The Nyquist diagram requires much labor but simple frequency plots of Ap, in decibel magnitude and in phase angle, can be used for determination of the safety margin below the instability levels at A/} = dB and = 180°. to w O u 1 < 8 0" ^N/2 i i t i i 1 1 * 1 -90° l l 1 1 1 Phase Margin * — 1 1 1 v 1 180° ^^. ">70° 1 1 — i 1 i i i i 1 , , — .I.. ..j- 10 50 100 500 1000 Frequency (kHz) Figure 9.16 Gain and phase margin. Review Questions 221 The gain margin is the decibel value of Afi at the frequency at which the phase angle reaches 180°. If negative, the amplifier is stable and can tolerate a theoretical gain increase equal to the margin, without regeneration. The phase margin is the angle of Ap at the frequency at which Ap reaches the 0-dB level or the unity magnitude ratio. Figure 9.16 shows about —9 dB of gain margin and 45° of phase margin for a particular audio amplifier. Usual design limits are considered to be — 10 dB of gain margin and 30° of phase. The frequencies at which these margins arc measured are far beyond the normal mid-range of audio use; for instance, f t ^ 34 kHz but the gain margin is measured at 440 kHz. Again, this shows the necessity for phase control and gain limitation by decompen- sating circuits at frequencies well beyond the operating band in feedback amplifiers. It indicates that reduced distortion has been purchased at the expense of problems associated with stability in greater bandwidths. 9.13 Comments Negative feedback is primarily used to reduce distortion in amplifiers and to make gain figures precise. We design excess gain into the amplifiers and sacri- fice this gain in using feedback in order to achieve desired results. With a large excess of internal gain, a large amount of negative feedback can be used and we obtain a precise overall gain without concern for variations of the internal gain figure. Widened bandwidth is an incidental result of using large amounts of feedback to reduce harmonic distortion. Summarizing the advantages obtained by the negative feedback process, 1. Reduction of nonlinear distortion. 2. Stabilized gain figures. 3. Improved frequency response. 4. Voltage feedback — lower output resistance. 5. Current feedback — higher output resistance. 6. Lower or higher input resistance. REVIEW QUEST/ONS 9.1 Define negative feedback; regeneration. 9.2 What is the feedback factor? 9.3 What is meant by closed-loop gain ? 9.4 Define voltage feedback; current feedback. 9.5 What is meant by series-input feedback; shunt-input feedback? 9.6 What conditions lead to increased gain with feedback? 9.7 What conditions lead to decreased gain with feedback? 222 Negative Feedback in Amplifiers 9.8 In negative feedback, what is the phase relation of the voltage fed back to the input voltage? 9.9 Equation 9.3 tells you whether the feedback is negative or positive. What do you look for? 9.10 How does Eq. 9.52 tell us that the emitter follower has negative feedback? 9.11 Under what conditions does feedback reduce distortion? 9.12 What form of feedback increases the output resistance of an amplifier? 9.13 What form of feedback reduces the output resistance of an amplifier? 9.14 What is the circuit connection used to increase the input resistance of an ampli- fier? To decrease it? 9.15 What is the effect of negative feedback on bandwidth? 9.16 What is the definition of/?? 9.17 When must /? be positive and when negative for negative feedback? 9.18 How docs the connection of the feedback circuit of an amplifier differ with an odd number of C-E stages from that with an even number of stages? 9.19 Why do audio amplifiers often have excessive bandwidth? 9.20 How does feedback affect the stability of amplifier gain? 9.21 How do you describe the form of feedback in an emitter follower? 9.22 How is current feedback obtained in a triodc circuit? 9.23 Why does an unbypassed emitter resistor reduce the gain of a C-E amplifier? 9.24 Trace out the feedback loop in Fig. 9.1 1. 9.25 Trace out the feedback loop in Fig. 9.12. 9.26 What is a Nyquist diagram? 9.27 Why should A$ avoid the value -1 ? 9.28 Why is the mid-frequency range concentrated at one point in a Nyquist dia- gram? 9.29 What is the Nyquist criterion for stability? 9.30 Plot the Afi values of Table 9.1 ; show that a circle is obtained. 931 What is gain margin? 9.32 What is the phase margin? 9.33 Name six advantages provided by negative feedback. 9.34 How do we pay for the advantages of negative feedback? PROBLEMS 9.1 For the black box feedback system in Fig. 9.17, if V, = 0.2 V, A = 20, and V = 1 V, find R, V,, V'„ and A'. 9.2 For the circuit in Fig. 9.17, we have A = 50, 0.03, and V' = 5 V. Find V„ V\, and A'. Problems 223 9.3 For the circuit in Fig. 9.17, we supply V, - 5 V, with A = -20 and = — 1.0. Find the output V' , V,, V\, and A'. 9.4 A l-V input signal for V, is used in Fig. 9.17 with A - 60, R = 0.07. What is V' , V f , and the gain A'l i; ^d> v\ V. Figure 9.17 9.5 An amplifier of three stages with voltage gains of —50, —15, and -10 has overall feedback applied with - -0.01. What is the overall gain with feed- back? 9.6 What value of (3 is needed to reduce the gain of the amplifier of Problem 9.5 to -100? 9.7 In the circuit in Fig. 9.7(a), R = 10,000 £2, R E = 1000 £2, h„ = 1 700 £2, and g m = 0.007 mho. Find the voltage gain; find /?,'; find R'„. 9.8 In the circuit in Fig. 9.8(a) we wish to incorporate 10 dB of negative feedback. Find R f if R, = 50,000 £2, R - 4000 £2, and A = -50. 9.9 An amplifier has /l p(rold) = 200 and/ 2 - 50 kHz. When we add negative feed- back with ft =0.10, what is the mid-frequency gain and what value of high- frequency band limit do we obtain? 9.10 In the circuit in Fig. 9.9, we have R„ = 10,000 £2, g m - 0.004 mho. With R, + R t = 100 k£2, find R 2 to give a gain of -5. 9.11 In the emitter follower of Fig. 9.10(a) we have R E = 5000 £2, g m = 0.0025 mho, and h„ = 1200 £2. Find the value of V bl for V, = 1.0 V. What is the gain? 9.12 An amplifier has a mid-frequency gain of 300 and/, - 500 kHz. We wish to raise the upper frequency limit to 5 MHz by the use of negative feedback. What gain will remain? What can you say about the gain-bandwidth product? 9.13 An amplifier has A = - 100 and R, - 5000 £2. What value of should be used to increase the input resistance to 50,000 £2? How would you suggest that the feedback circuit be arranged? What is the gain with feedback? 9.14 A transistor with h„ =- 1000 £2, h f , = 60 is used in a C-E circuit with R - 2000 £2, R £ (unbypassed) = 700 £2. Find /? and the gain with the feedback present. 9.15 Find the input impedance of the amplifier of Problem 9.14, with and without R E present. 9.16 An amplifier without feedback has A, = -2700. With feedback, the gain A', Negative Feedback in Amplifiers is -97. What is the value of /? being used? How much feedback in decibels is used? 9.17 Feedback of 15 dB is added to an amplifier with internal gain A 250. What is the value of fi required, and what is the gain with feedback? For the same output voltage, what will be the change in input voltage? 9.18 An amplifier has A,. = -80 and V„ -= 100 V with 8 per cent harmonic distor- tion. We wish to reduce the distortion to 0.5 per cent. What value of fi should be used, and what input voltage is needed to give the same output as before? 9.19 The gain of an amplifier without feedback is 100. The output resistance without feedback was 1500 fi. Plot a curve of output resistance with negative voltage feedback as a function of /? over the range /? = 0.005 to /? = 0.15. 9.20 An amplifier has an internal gain of 37 dB and at 50-V output has 1 1 per cent distortion. Feedback is to be used to reduce the distortion to 1 per cent. (a) What gain will be obtained ? (b) What input signal must be supplied for the same output? 9.21 An amplifier has an internal voltage gain A - 512 and an output of 12 V. Feedback is added until 0.95 V is required as input to give the same output! Find the fi being used. 9.22 An amplifier in an electronic voltmeter must have a voltage gain of 100 within 0.5 per cent but the internal gain may change as much as 12 per cent due lo component changes. Determine the value of /? needed to meet the guarantee and the needed internal gain. 9.23 With negative feedback an amplifier gives an output of 10.5 V with an input of 1.12 V. When feedback is removed, it requires 0.1 5-V input for the same output. Find the value of /? and of the gain without feedback. 9.24 An RC amplifier has three identical stages, with/, = 48 Hz, h = 140 kHz for each stage. The overall internal gain is -450 and fi = -0.05 is applied. Deter- mine/', and/j for the amplifier with feedback. 10 Integrated Amplifiers Circuits that eliminate the scries blocking capacitor arc said to be direct- coupled. The mid-frequency range is thereby extended down to zero fre- quency. More importantly, by removal of the bulky blocking capacitor the amplifier size is reduced and it becomes possible to integrate an amplifier circuit on a silicon wafer along with its transistors and diodes. Such mono- lithic construction leads to small size, high reliability, reduced cost, and offsetting of temperature effects. Problems arise because of bias voltage needs but these are met by use of dual power supplies or by special circuit design. By adding negative feedback the operational amplifier or so-called "op amp" has evolved. With this device we closely approach an ideal element having constant and controlled gain. In addition, high input resistance and low output resistance are achieved. Such gain elements can be cascaded without much concern for the effects of variable loads at the output. 10.1 The Integrated A mplifier In Fig. I0.l we have the circuit of an integrated direct-coupled amplifier. With negative feedback added externally, the circuit becomes a stable general-purpose high-gain amplifier. The complete circuit contains 10 transistors, 2 diodes, and 16 resistors and 225 Sk 9°" or CH + 00 ♦— WW- t— WW -WW- aT —<ee, 2 _o- o ♦-WW- <*: aT Mwv- j< o ^ a a c» o. -ww a 3 o The Integrated Amplifier 227 is built on a chip of silicon approximately 1 mm 2 . This chip is enclosed in a 12-terminal package about 1 cm in diameter and £ cm high. While the amplifier appears to be complex, the circuit functions can be readily explained. Transistors Q, and Q 2 constitute an emitter-coupled differential amplifier stage. Input to terminal 3 gives an output in phase with ihc input and A is positive; input to terminal 2 inverts the signal or gives a reversed phase output and negative overall gain, — A. Terminal 4 is at — V cc and serves as the ground connection. The outputs from Q, and Q 2 drive a second emitter-coupled differential pair at Q 3 and Q t . The output is taken from Q t and drives Q s , which supplies the base input for Q, . This transistor furnishes the amplifier output at terminal 9 as an emitter follower, used to ensure a low output resistance. Transistor Q it through its action on the currents of Q } and Q it cancels shifts in dc level that would occur with changes in dc supply voltage. A decrease in V cc causes a decrease in the voltage at the emitters of 3 and Q«. This negative-going change in voltage acts on transistor Q 5 with its emitter output going to transistors Q 1 and Q 9 , and less current passes these transis- tors. But less current in Q } , Q„ and Q t raises the collector voltages of these transistors, canceling most of the original downward shift from V cc . Tran- sistor Q 6 is a constant-current control for the first differential pair. The output circuit of Q 9 and Q l0 shifts the dc level at the output so that it is substantially equal to the zero level at 2 or 3 with zero signal. All transistors arc manufactured in the same operations and while Q 5 , Q s , g„ and Q 9 could be eliminated without reduction in the overall gain of the block, their presence adds little to the cost and much to the overall stability of output with varying supply voltages. Made as a monolithic element on silicon, the transistor characteristics are more nearly the same than when discrete units are assembled. The resistors are formed on the chip as well and the connection costs arc not increased by the circuit complexity. The two transistors of each differential pair will cancel common varia- tions. Since the two transistors are formed on the same chip with only a few thousandths of a millimeter separating them, temperature differentials between transistors are negligible and the effects of temperature changes on transistor characteristics are canceled. There is a great variety of such integrated circuits available. In general, they consist of four stages and Fig. 10.1 illustrates these. The first stage is the differential amplifier of Q, and Q 2 , with differential output; the second stage is a cascaded differential amplifier with sindc-ended output, composed of Q 3 and Q t . Third comes an emitter follower Q b to lower the dc voltage level back toward that of the input, and the fourth stage is the output at £?, - A study of the elemental circuits employed and some of the applications 226 228 Integrated Amplifiers of these "gain blocks" are the objectives of this chapter. Additional informa- tion on integrated circuit processing will be provided at the end of the chapter. 10.2 The Differential Amplifier As can be concluded from the previous description, the differential amplifier is the basic element of the integrated amplifier. Drawn in Fig. 10.2, the differential amplifier circuit is symmetrical about the vertical dashed line a-a' and identical parameter changes on each side are balanced out. Direct-coupled amplifiers are unable to distinguish between changes in the dc value of a signal and temperature-caused changes in v BE , h FE , and the reverse saturation current and so the output current will drift with tempera- ture. In the differential amplifier the two transistors and the load resistors form a balanced resistance bridge at zero signal. A simultaneous change in v BE of the two transistors will change the collector currents; the voltages at A and B will change identically but the difference A — B will not be affected. Temperature drifts can be limited to effective input values of 3 /iW per °C (2 nV per °F). The circuit is well suited to integrated unit production because the simultaneously produced transistors and resistors will be matched closely. Equality of resistors is an important factor that can be easily achieved, whereas to produce resistors of an exact magnitude is difficult in processing. U & differential input voltage is applied, the inputs K, and V x will be equal in magnitude but of opposite polarity. With equal transistor parameters, one collector current will increase and the other will decrease. Voltages at A and B change up and down so that there is a voltage V„ between A and B. The changes in the respective collector currents are illustrated in the transfer curves in Fig. 10.3. Since the sum of the two currents remains constant, there is no signal voltage change across R E . If a signal is introduced to both transistors in a common mode, with both inputs being equally positive or in phase as an example, the collector currents increase identically and the bridge remains balanced with equal voltages at A and B. The output V„ remains zero. The current in R B does change with a common-mode input, however, and a common-mode signal appears across R E . The equivalent circuit is drawn in Fig. 10.2(b), in a form that emphasizes the bridge action of the amplifier. With identical transistor parameters we can write the circuit relations as F, = (R, + h u )l„, + R E I, Vi = (.R, + A,.)/*, + *,/. /. = /., +/„=£ h rJb, + h/Jb, (10.1) (10.2) (10.3) (a) W (b) Figure 10.2 (a) The differential amplifier; (b) equivalent circuit. 229 230 Integrated Amplifiers c | 12 8 4 4 -8 - 12 fcl 'c 2 \ / \ / / \ / \ 8 12 4 4 Inpul (mV) Figure 10.3 Transfer curve for a differential amplifier. Using Eq. 10.3 in Eq. 10.1 and 10.2, we arrange the results as V t - (/?, + hjlt, + h fl R E I bl + h f .R E l b , (10.4) V 1 = (R, + /,,.)/>, -1- h„R B I b , | h f ,R E I bl (10.5) Subtracting, we have Vr-V%= (*, + l'„)(h, ~ I J However, with balanced or matched transistors a change in I b , is a negative change in /„„ or / tl = — I h , and so V,-V z = 2{R, + AJ/ ti from which Similarly we can find that '•■ 2(R, + h„) I - v* - V * lb ' 2(R, - /;„) (10.6) (10.7) The voltage between A and fi at the collector connections is v. = hM* - hf.RJ,, Substitution of the current values from Eqs. 10.6 and 10.7 yields v.=- with a differential gain as A«- v x -v x I | f' _ 8«Rl 1+A hi. (10.8) The Differential Amplifier 231 With y, and V 1 opposite in polarity, V x = — K 2 , we have an output V Q . If V x and K 2 are equal in magnitude and positive, the output is zero. We have stated that no signal voltage appears across fl £ with differential input voltage; confirming this is the absence of R e in the output voltage expression. It is evident from either Eq. I0.6 or Eq. I0.7 that the input resistance to either base is Hi = & =£ - 2(*. + h„) (10.9) This represents the series resistance of the path through the transistors and V x and V 1 ; the signal currents bypass the emitter resistor and it could be eliminated from the equivalent circuit because no signal voltage appears across it. When the output is taken from one collector to ground, the operation is said to be single-ended and the gain is one-half of the differential gain, as K„ (single-ended) — 2 ' S (10.10) The differential amplifier circuit becomes an emitter-coupled phase inverter when the signal is applied to one input and the second base is grounded. The output voltages at 2 and 2' are of equal magnitude and 180° in phase. This is shown in Fig. 10.4. Vcc 9+ -o2 -o2 + -«2 \R B V, EE Figure 10.4 An emitter-coupled phase inverter. 232 Integrated Amplifiers 10.3 Rejection of Common-Mode Signals The differential amplifier tends to cancel effects common to its two sides and this action extends to signal voltages that are equally introduced in phase (not oppositely, as with differential plus and minus signals). Such common- mode signals are frequently caused by ac variations in the supply voltage or by voltages from stray magnetic fields in the ground or signal leads. The common-mode signal is introduced equally to transistors Q, and Q z as shown in Fig. 10.5 and these signals arc usually unwanted in the amplifier output. In Fig. I0.5 we have the two inputs to the amplifier as K rf for the dif- ferential input and V c for the common-mode input. With differential input the transistor voltages are equal but plus and minus, or V,, = — V lt . For the common-mode signal, V u = V lt and y c - v„ v c = v H By adding. V,= "„ + v„ (10.1I) With a pure differential signal and V,, = — V,„ the common signal is zero. Differential- (Z\y ( Mode Signal \~S d Common- Mode Signal Figure 10.5 Showing a common-mode signal. Rejection of Common-Mode Signals 233 As long as we have a perfectly symmetrical circuit, the common-mode signal will be canceled but we want to know how to maximize the rejection of common-mode signals when circuit unbalances occur. If a positive common- mode signal causes the transistor currents to rise, as would be expected with the npn units in Fig. 10.5, the voltage drop across R E also rises. This increased emitter voltage subtracts from the input signal and causes negative feedback, reducing the gain for the common signal. Differential-mode signals are not passed through R E and no differential voltage appears there. We usually want the common-mode signal to be rejected so that a high value of R E for feed- back is indicated. + y cc Figure 10.6 Single-ended differential amplifier. We often wish to have one side of the output at ground potential and use a single-ended output circuit, as in Fig. 10.6. Because of the loss of circuit symmetry, a common-mode signal will produce some output, although there will be a substantial reduction in gain for the common-mode signal. A measure of the rejection of the common-mode signal in the output is given by the common-mode rejection ratio, defined as CMRR — differential-mode gain common-mode gain (10.12) The output consists of differential output and common output so that V.-AJTi + AjT, (10.13) 234 We can develop a useful relation as ~ A « V <V -* cmrrF,) Integrated Amplifiers (10.14) Since A^Vj is the desired output, we readily determine the effect at the output by the additive term (l/CMRR)(K c /K d ). To obtain the CMRR for the circuit in Fig. 10.4, we split the circuit down the a-a' line; since R E appears in each half, it is shown as 2R E in Fig. 10.7. It becomes R E when paralleled in the actual circuit. Each half is a C-E transis- tor circuit with an emitter resistor 2R £ and the gain is A, c = —hf,R L h„ 4- R, — 2h fe R l -gm*L l+£+2g m R t: (10.15) With Eq. 10.8 for the differential gain we can calculate the CMRR value for the circuit as CMRR = 2g m « E (10.16) This result confirms the assertion that R E should be large for a large value of CMRR. Example I: With a transistor having g m — 0.0025 mho, what value must R E have to obtain a CMRR value of 40 dB? To obtain CMRR as a ratio, 40= 20 log CMRR logCMRR = ^ = 2 CMRR - 10 2 = 100 = 2g m R E from which *« = 2x2.5 ( "xl0-3 = 1 3 ! = 20 - 00QQ Example 2: We have input voltages of V,, = 50 piV and V,, = —50 /*V. The difference-mode gain of the amplifier is A„, — 1000 and the CMRR value is (a) 100 (40 dB); (b) 10,000 (80 dB). Calculate the output. We find Then V t - V u - V„ = 50 - (-50) - 100 jiV = 0.1 mV V - V « + V " - 50 ~ 50 - a 2 2 U Rejection of Common -Mode Signals 236 + o — vvft — H Vi Qi 1 -AMAi o + I Figure 10.7 Circuit analysis for CMRR. The differential signal output is V = A*V t = 10 3 x 0.1 x lO" 3 = 100 mV and we have zero common-mode output. Example 3: For the same amplifier we now have signals V u — 1 .00 mV I V„ = We find and V h = 0.90 mV. V t = V h - V,, = 1.00 - 0.90 = 0.10 mV as the differential signal. The common-mode signal is (a) With CMRR = 100, we use Eq. 10.14 to find 1 V c .wxm(i 100 W) - ■» 5mV For the same differential input as in Example I, the output has been increased 9.5 per cent by the presence of the common-mode signal, (b) With CMRR = 10 4 , we again use Eq. 10.14 to find y„ = 10' X 0.10 (l -I -rgj^y) = 100.095 mV With the larger CMRR the error in the output signal caused by the common- mode voltage is only 0.095 mV, or about 0.1 per cent. 236 Integrated Amplifiers 10.4 A Constant-Current Circuit for R E For differential-mode signals we expect the current in R E to be constant. We would also like R E to be very large to give us a high value of CM RR. We can achieve these results by use of transistor Q y in the constant-current circuit in Fig. 10.8. Looking at the / 3 series circuit, (R 2 + /?,)/, + V D - V EE = after neglecting I B as small. If V EE > V D , then we have for / 3 /,^ (10.17) Around the base-emitter circuit of Q 3 we can write R>L + Vbe, = *»/, + V„ and using I } from Eq. 10.17 n i Rl' ee _i_ y y 1 " _ R _ R ' ' D 'BE, If we select diode D to have a voltage characteristic equivalent to that of the base-emitter diode of g 3 , then V D = V BE , and (10.18) h = (10.19) RARi \ R 3 ) This expression for transistor current contains no transistor parameters and is a constant. Figure 10.8 A constant-current bias transistor. The DC Level Shifter 237 Transistor Q, is a current feedback amplifier and so has a large output resistance at the collector. This may approximate several megohms. This gives a very large effective R e value in Eq. 10.16 and a very large CMRR value. The value of V BE decreases about 2.5 mV per °C (1.5 mV per °F) but the diode can be chosen to vary similarly and the cancellation of V n and V BK in Eq. 10.18 can be achieved at all usual temperatures. As a result, /„ is inde- pendent of temperature. These circuits appear at Q 6 and Q 1 in the emitter leads of the differential amplifiers in Fig. 10. 1. A simpler but less accurate constant-current circuit is formed by a transistor with a fixed voltage reference applied to the base. The collector current is then I c = h rE I B and constant. The accuracy of current control is dependent on constant v BE and h n values. This is the function of Q 9 in the amplifier in Fig. 10.1. 10.5 Voltage References We have just discussed an application in which a transistor was biased by the forward-voltage drop of a diode. The forward-biased silicon diode may be assumed as presenting a constant voltage, about 0.7 V, regardless of current. To obtain greater voltages, several diodes may be connected in scries. By choice of the temperature characteristic of the diode, temperature compensa- tion can be added to the function of a voltage reference diode, as shown in Sec. 10.4. These drops are smaller than can be obtained by use of a Zener diode and, more importantly, a diode such as D in Fig. 10.8 can be processed in the same steps and with the same materials as are required for the emitter-base junction of a transistor on the silicon chip. 10.6 The DC Level Shifter With each stage deriving its base input voltage from the preceding collec- tor, the dc voltage level of each base rises with respect to ground, as one progresses through a direct-coupled amplifier. It is therefore necessary to shift the voltage level back down to obtain an output at which zero output voltage corresponds to zero input voltage. Using resistors and transistors, the <lc level shifter in Fig. 10.9 is well suited to integrated circuit production methods. Input is supplied to Q„ which operates as an emitter follower. Signal output is taken from Q„ also an emitter follower, to provide a low output resistance. Transistor Q 2 is a constant-current device, with its base supplied by a fixed reference source; therefore I c = h rE l B and is constant. With current l E 238 Integrated Amplifiers t+Yrr Input o—PT \j Voltage Reference Output Figure 10.9 DC level shifter. also constant, since / £ ~ l c , the drop in /?, is constant. Along the signal path shown we have y BE , + R\1b + y B E, = K constant volts We call AK,„ a change at the input and AK 0U1 the resultant change at the output. Voltages with no signal at input and output are K,„ and V oal . Then we can write through the signal path AK ln + K lB - K volts = AV oat + V OM A change in the input is transferred directly to the output as AK,„ - AK 0U , but the no-signal voltage level at the output is lower than that at the input because K„ - K = V m (10.20) A level shifter of this kind appears in Fig. 10.1, using Q„ and Q 9 with 0, o for output. 10. 7 The Operational Amplifier When negative feedback is added to an integrated dc amplifier of large internal gain, we have an operational amplifier or op amp. It was originally given the operational name because of its use in performing the mathematical The Operational Amplifier operations of addition, integration, and differentiation but its applications are now much more general. The basic circuit is that in Fig. 10.10(a). The amplifier may have a number of stages and resistor R f , or some other circuit element, supplies voltage-shunt feedback around the gain element, stabilizes the gain, and lowers the output resistance. We define the internal gain as (10.21) A y . We shall require that gain A be very large as a condition of amplifier design, perhaps A > 10*. This permits us to say that V, = at the amplifier terminal at 1. To justify this statement, let A = 10 4 and V„ = 10 V; then V\ = 1 mV. With large A, we are also saying that A/} > 1 in the usual feedback amplifier expression. With V, = 0, however, the current to the amplifier must be negligible as well, or /; = at terminal 1. Then a current summation there gives /, » -h (10.22) With the voltage V\ as zero, these currents can be stated / ^ Using Eq. 10.22 and the gain with feedback is v. V, R x This is the basic gain relation of the inverting operational amplifier. (10.23) /, ww- A/WV- o+ o + o- <a) «>) Figure 10.10 (a) The operational amplifier; (b) the noninverling form. 240 Integrated Amplifiers The stability of the gain with feedback is dependent only on two resis- tances, or impedances in general, and the value of the gain can be easily adjusted. Note that the gain with feedback is independent of the internal gain provided that the internal gain is made large. Equation 10.23 is a result of A being large, as was Eq. 9.1 1 : I A'=* J (10.24) so we see that for the inverting operational amplifier Using an amplifier integrated on a silicon chip and adding two resistors and a power supply, we have a stable package of gain. The package will have high input resistance, low output resistance, and a wide and controllable bandwidth. The operational amplifier employs the circuits of the preceding sections in functions somewhat as shown by the typical arrangement in Fig. 10.11. Because of the differential amplifier at the input, there arc two input connections available: one resulting in an inverted output or a gain —A' and the other giving a noninverted output and gain | A'. This adds further flexibility to the operational amplifier. When not used, the second input is Input Feedback Differential Amplifier Differential Amplifier Emitter Follower DC' Level Shifter Constant Current Output Amplifier ■*- Output Constant Current Figure 10.11 Functions of an integrated operational amplifier, illustrating the dc levels. The Operational Amplifier 241 applied to the positive gain input terminal of the amplifier. The feedback is returned to the negative input terminal so that K,-t-^ to ground. There is a differential input V, - V { and the output of the amplifier is V ^A{V,-V f )^A(y,--^- T V^ (10.25) and the gain is A vr i + AR, (10.26) R, I R f If A ^> 1 as we have required, then the gain with feedback reduces to j, _ R, + R/ A —rT- (10.27) This approximates a positive equivalent to Eq. 10.23 and becomes equal when /?,>/?,. Example 1: The circuit in Fig. 10.10(a) is used for signal inversion, with A = -100,000, R, = 1000 a and R, = 10,000 Q. The gain is A' = -& = 10,000 = -10 R, ~ 1000 Since ft = — R,IR f = -0.1, we could use the accurate feedback expression -A -10 s -10 s A' = —a _ ~'» _ ~~' u _ _q goon 1 + Aft ~ 1 + 10 5 X 0.1 ~ 1 |- 10* which shows that when A = — 10 s , we can certainly neglect I < Aft. This is equivalent to saying that V, = 0. Example 2: We use the circuit of Fig. 10.10(b) in the noninvcrting connec- tions. The gain is ., _ /?, + R f _ 1000 + 10,000 _ , , n A ' ~~R, iooo uu Since R = i?,/(/?, t R f ) = 0.091 1, then the accurate feedback expression gives A'=* 10 s = 10.999 1 + Afi 1 + 9090 which again confirms our requirement that A be large. 242 Integrated Amplifiers The Integration Operation 243 10.8 The Unity-Gain Isolator One of the simplest applications of the operational amplifier is the unity-gain circuit in Fig. 10. 12, useful in isolating one circuit from variations that may occur in a load circuit. From the circuit, r t +r t - v (io.28) But V\ S so that V, = V (10.29) and the output voltage follows the input signal, without a phase reversal. Since the output resistance is low, needed output currents can be obtained without loading an input circuit at 1,1, and the circuit is a buffer. 10- 02 Figure 10.12 Unity-gain isolator circuit. 10.9 The Summing Operation Several input voltages may be simultaneously operated upon in the opera- tional amplifier in Fig. 10.13. Current /, represents the sum of the three current components through R„, R b , and R c . That is, -/ 2 = /, and Rf Ro &b R c and so u r " + R/ b ■%"•) (10.30) and the output voltage is equal to the weighted negative sum of the several inputs. If R„ = R„ = R c , then R, Vo = -%(V. V b + V c ) (10.31) If R f = R„, the output represents a negative summation of the input voltages. r Figure 10.13 A summing amplifier. 10. 10 The Integration Operation By use of a capacitor in place of R f , the operational amplifier will perform an integration of the input voltage. An integrator circuit is shown in Fig. 10.14. The result of integration can be understood if we recall that the current- voltage relation for a capacitance, connected between V and ground poten- tial at 1, is K = lj'/ 2 A (10.32) (a) 1 V u- 1 1 V (h) (c) m Figure 10.14 (a) Operational amplifier as an integrator; (b) input rectangular pulse; (c) output integral, \jRC = 1 ; (d) output integral, l/RC = 0.1. 244 Now we have previously shown that /■ = -h because /,' S 0. Since V\ = 0, we have said / =£ Integrated Amplifiers (10.33) Because of Eq. 10.33, / -- V < Substitution of this result in Eq. 10.32 gives (10.34) (10.35) as the output-input relation for the operational amplifier. The output voltage is the integral of the input, with a scale factor of — \/R,C. If we make /?, = 1 MSI and C = 1 fiF, we have R,C = 10 s X 10" 6 = Is and the scale factor is — 1 . Since RC has units of time, in seconds, we can use the RC scale factor to scale problems using a time variable. The integration operation is demonstrated on the step input in Fig. 10. 14(b), the result being of ramp voltage form as the capacitor charges. If we had made R = 0.1 MQ, then l/RC = 10 and the result would plot toward — 10, reaching - I V in one-tenth of the time, so that time is scaled by changing RC. Figure 10.15 shows a multiple input integrator with different scaling factors, as might be used in an analog computer. The differentiating operation, opposite to that of integration, can be performed by using C for R, and a resistance as R f . We encounter noise problems in differentiation, however, and the operation is avoided. Figure 10.15 Use of different scale factors in integration of several signals. A Millivoltmeter 246 10.11 The Comparator One useful application of the differential amplifier is that of a comparator of the magnitudes of a signal voltage and a reference voltage. The voltage comparator in Fig. 10. 16 is basic in digital computer applications. Its action is demonstrated by the transfer curve of the differential amplifier in Fig. 10.3. When the input signal is slightly greater than the reference voltage, the output swings to saturation; when the input signal is slightly less than the reference voltage, the output swings to saturation on the other side and the output voltage reverses. A comparator is used in digital voltmeters, where the input voltage is compared with an internally generated ramp voltage. The cycles of an oscillator are counted from turn-on, with the count being stopped with a signal from the comparator at equality between the unknown and the ramp voltage. If the ramp wave rises at 10 mV per millisecond and the oscillator is at 10,000 Hz, the display will read 1 500 counts for an input voltage of 1 .5 V. Placement of the decimal point will cause the meter to read 1.500 V. Input o Figure 10.16 Basic comparator circuit. 10.12 A Millivoltmeter In Fig. 10. 17 another application of an operational amplifier yields a niillivoltmeter. The instrument M may be one of 1-mA full-scale deflection. Since the operational amplifier gain expression yields R, '' (10.36) R>R V, So we have A- R f V, - R,R„ This is the basic equation for the circuit and states output current per volt of (10.37) 246 Integrated Amplifiers 100 kfl AAIW- Figure 10.17 A millivollmcter using an operational amplifier. input. If we measure /„ in milliamperes, then V, must be measured in millivolts so we have units of milliamperes per millivolt. With the circuit values shown in Fig. 10.17, we have 10' U 1 TO 10 5 x 10 so that we shall have a reading of I mA, or full scale on the instrument, for 10-mV input to the amplifier. The full-scale value in millivolts can be readily changed to other millivolt values by changing /?, or R f . 10. 13 Frequency Compensation As a feedback amplifier of many stages, the operational amplifier can have gain instability and oscillation at the high frequencies. The several stages have input capacitances for the transistors and the gain falls off or "rolls off" above limit frequencies fixed by these capacitances and associated resistances. Some amplifiers are internally compensated for stability but others require external R and C components so that the designer can choose his own bandwidth and stability margins. A typical uncompensated gain curve for an operational amplifier is shown in Fig. 10.I8, without feedback. The curve is drawn by use of the asymptotes of the frequency response curves, for simplicity in sketching. Uncompensated, the amplifier shows 60 dB of gain to the first limit frequency fi at about 200 kHz. Two more limit frequencies are determined by the RC combinations of the several stages at/' 2 and/:'. Each combination causes a rate of gain fall of -20 dB per frequency decade and these rates are additive, reaching -60 dB per decade above f% at about 20 MHz. We want to obtain 20 dB of closed-loop or feedback gain, thus using 40 dB of feedback = (l - AR) dB. We draw the horizontal line at 20 dB and discover the gain to be limited at about 8 MHz and that the amplifier curve is The Slew Rate 247 Uncompensated / 20dB/Deeada 40 dB/Uecade O -20 - 60dB/Decade Frequency Figure 10.18 Uncompensated and compensated amplifier performance. falling at a rate of -40 dB per decade. From our study of feedback amplifiers we know that a rate of - 20 dB is associated with a phase shift of ±90° and is stable and that a rate of — 40 dB per decade represents a phase angle of _^180° with potential instability. From the discussion of gain and phase margin we know that our gain curve should cross the 0-dB gain line before the phase angle reaches 180°. For an amplifier to be stable, the gain curve should cross the 0-dB gain line at a slope not greater than — 20 dB per decade. We must compensate the gain curve by introducing a series RC circuit across appropriate terminals designated by the amplifier manufacturer. The roll-off of a simple RC circuit is — 20 dB per decade and we design the compensating circuit to have a corner frequency of about 7 kHz, sufficiently low that the -20-dB slope extends to dB before we reach the/', frequency. This is shown as the heavy line in the figure. The gain is less than dB before the phase angle of the gain reaches 180° at/', and the amplifier will be stable. Instead of reaching a bandwidth of 8 MHz, which might have been hoped, we now have a bandwidth of only about 400 kHz; however, this is still slightly wider than that of the amplifier alone. This is the price we must pay for stability. 10.14 The Slew Rate Due to the charging time of the input capacitances of the transistors, the rate of rise of voltage is limited when a step input is applied to an operational amplifier. This maximum rate of voltage rise is called the slew rate. Consider the basic amplifier circuit in Fig. 10.10. The full input voltage step appears at input I because the output feedback from V cannot respond 248 Integrated Amp/Wets |f = Slew Rate Figure 10.19 Effect of the slew rate on rise or output voltage. instantly. This large value of input voltage drives one or more stages of the amplifier into saturation and the transistor capacitors are charged. As shown in Fig. 10.19, output V„ can rise only as fast as the internal capacitances can discharge and so we have the slew rate, given by 5 = AK„ A/ (V///S) (10.38) This is a specification supplied by the manufacturer of the amplifier. The maximum rate of change in a sine wave is a function of frequency; and the amplifier slew rate may limit the amplifier in following a large signal at high frequency. The maximum rate of change of a sine wave occurs at the zero crossing and the slew rate should be greater, or ^f > W. (10.39) where /is the frequency in megahertz, V mtx is the peak output voltage in volts, and the slew rate is in volts per microsecond. The slew rate is primarily of concern in selling a limit on the lime in which the amplifier may be switched from on to off. Example: Given an operational amplifier with a stated slew rate of 10 V per //sand with a supply voltage of V^ = 15 V. In switching, the output will go from =c to = 15 V as on to off conditions. The time for this opera- tion is determined by the slew rale as '* S ~ 15V 10 V///s = 1.5^ With a sine wave of V a = 15 V peak value, the slew rate will limit the response of this amplifier to /- 10 TxV, o(max) 2tz x 15 -0.106 MHz If the peak of the sine wave is only 1 V, then the expression above shows that the response band would extend to 1.59 MHz. Definition of Terms 249 10. 15 Offset Voltage and Current With both input terminals grounded, a practical operational amplifier will develop a small output voltage, due to inherent imbalance in the circuits. The input offset voltage is defined as that voltage that must be supplied to one of the inputs to reduce the output voltage to zero. The value of the input offset voltage V„ can be determined from the output offset as ^1 v r„ = (10.40) as in Fig. 10.20(a). The offset voltage V u is typically a few millivolts; hence amplifiers with appropriately small values should be selected. A difference in base bias currents at the input of an operational amplifier is called bias current offset. The effect can be reduced by insertion of a resistor R 2 in the circuit having excess current as in Fig. 10.20(b). The resistor should be R? R,+Rf (10.41) 9 WW Q WW (a) (b) Figure 10.20 (a) Input offset voltage; (b) input offset current. 10. 16 Definition of Terms There are a number of terms used in amplifier specifications that need to be understood, and we gather some of them here: Bandwidth. The frequency at which the voltage gain of the amplifier is 3 dB below the voltage gain at mid-frequency. Common-mode Voltage Gain. The ratio of the ac voltage between the two output terminals to the ac voltage applied to the two input terminals con- nected in parallel for ac. 250 Integrated Amp/i/iers Differential-mode Voltage Gain. The ratio of the voltage change between two output terminals to the change in voltage between the two input ter- minals. Common-mode Rejection Ratio (CMRR). The ratio of the differential- mode voltage gain to the common-mode voltage gain. Differential Voltage Gain — Single-ended Output. The ratio of the change in output voltage with respect to ground at either output terminal to the change in voltage between the two input terminals. DC Dissipation. The total power consumed by the device under zero input signal and zero output conditions. Input Offset Current. The difference in the currents at the two input ter- minals for equal applied voltages. Input Offset Voltage. The dc voltage that must be applied between the input terminals to obtain equal quiescent voltages at the output terminals. Maximum Output Voltage. The maximum output voltage swing that can be achieved without distortion of the output waveform at the peak. Single-ended Output. An amplifier with output taken from only one of the two input terminals. Slew Rate. The slew rate is the maximum rate of change of output voltage with large signal inputs. 10. 17 The Darlington Compound Transistor Two transistors can be assembled on a common chip in the manner of an integrated circuit, giving us a device called the Darlington compound transistor, shown in Fig. 10.21. By the usual transistor current relations, /, and / ; are But l bl is the emitter current of 0, so that h, - + h f ,)l, and so h = A/«(l + h f .)I, (10.42) (10.43) The Darlington Compound Transistor 261 Addition of Eq. 10.42 and 10.43 gives for the load current 4 = [h fei + hfM + h fll )]l t The current gain is available from this expression as Figure 10.21 The Darlington compound transistor. (10.44) A, = -j- = h fet + hf„h f „ = h fe ,h fc (10.45) The last expression is simple and provides a fair approximation. The base-emitter circuit of Q 2 acts as the emitter resistance of g, and by use of the C-C relation we have R„ = K -I (1 i hfitom ( 10 - 46 ) Transistor Q z provides negative current feedback to Q i and raises the input resistance at 1,1. Using the relation between current gain and voltage gain as ^loid A v = -A, *.„ put and Eq. 10.46, the voltage gain of the Darlington connection is R -h r " Hf "h lt , I ■hf.M.. hi,. (10.47) which is just that of a single transistor in the C-E circuit. By use of the Darlington connection internally made in the transistor, however, we have a single unit that gives the voltage gain of a single transis- tor, but with a materially increased input resistance. The Darlington com- 252 Integrated Amplifiers *V. Conslanl-Currcnt Transistor Figure 10.22 Darlington amplifiers added at op-amp inputs. pound transistor is frequently added at the differential inputs of an operational amplifier to raise the input resistance. This is indicated in Fig. 10.22. 10. 18 The Cascode Amplifier As an example of the design of special circuits in integrated form, we have the cascode amplifier in Fig. 10.23. As simplified in Fig. 10.23(b), the signal circuit of Q x and Q } consists of a C-E transistor followed by a C-B stage. Transistor Q z is employed to vary the gain of Q 3 , through control voltage applied to terminal 10. The load of Q, is that of the emitter circuits of Q 3 and Q 2 . That is, '* 2(l+A Al ) = 2 ft (10.48) and is therefore small. The voltage gain -g m R,, of Q, is quite low. With a very low gain, however, the Miller effect cannot appreciably affect the capacitance at the input of Q x and so that transistor has a very large f z limit frequency and a large bandwidth. For the C-E stage the gain is approximately The gain of Q } , however, is that of a C-B amplifier A„ = g m ,R (10.49) Silicon Integrated Circuits 263 To Q 2 V cc |o- € l(— o *h 3 2 2 (a) (b) Figure 10.23 (a) The MC 1550 integrated circuit; (b) simplified cascode circuit. The frequency range of a C-B amplifier is also wide, with/, = h fc f f , and so we have a circuit with three transistors on the same chip, in one package, with the input resistance of a C-E transistor but with a bandwidth of/, =/ r of the transistor. The complete package in Fig. 10.23(a) is used as a small-signal high- frequency amplifier. 10. 19 Silicon Integrated Circuits The techniques of impurity diffusion from a gas, masking, oxidation, and metal deposition have made possible the production of complete circuits integrated into a chip of silicon. Reliability is high because interconnections are formed with the circuit elements. Size is drastically reduced and the response can be controlled because lead lengths and stray capacitances are constant. Figure 10.24 illustrates how the basic manufacturing techniques are applied in a simple integrated circuit. A />-silicon wafer, large enough for several hundred circuits, is the starting point. An n impurity is diffused through a photoresistant mask to form the n pockets in Fig. 10.24(b). The/wi diodes to the wafer will be back-biased and their resistances will isolate the circuit elements. Additional masking and etching provide holes in another coat of photoresist through which the p-base areas in Fig. 10.24(c) are 254 Integrated Amplifiers B C p Water (a) SiO, A>W p P H( )fei fesd! «1 (d) C B E W Aluminium 2 3 X 4 SiO, (e) (0 Figure 10.24 Steps in integrated circuit production. diffused. In the next step an n emitter is diffused into the base for a transistor at A. The result appears in Fig. 10.24(c). Finally the surface is oxidized, followed by etching of holes for the connections, and aluminum is deposited through a mask to form the leads as in Fig. 10.24(e). The electrical circuit is shown in Fig. 10.24(f). An npn transistor has been formed at A; a series resistor ofp material is at B, with a capacitance at C using the oxide layer as a dielectric. The steps in production are basically the same as those required to make a transistor and this is a production benefit. All transistors produced are virtually identical, although there may variations from one batch to the next. Diodes, resistors, and capacitors can also be formed and junctions given alternate usages as capacitances under back bias and resistances under forward bias, as well as serving as voltage references. When using discrete components, the active device, transistor, FET, or vacuum tube is considered a high cost item and resistors and capacitors arc used in preference. In the integrated circuit, cost is a function of circuit area and independent of the number of components per unit area and a transistor can be produced as cheaply as a passive element. New circuit designs become possible, using transistors to perform functions that might otherwise be carried out by passive circuit elements. The use of the constant-current transistor instead of a resistor in the emitter circuit of the operational passive Elements 255 amplifier is an example of this. The constant-current circuit acts as an almost infinite resistance and greatly increases the common-mode rejection. An actual large R e would require an excessively large value of emitter supply voltage V EE and would waste power. 10.20 Passive Elements A circuit capacitance can be developed between collector and base elements formed in the integrated circuit. There is also a capacitance in the reverse- biased diode to the wafer. The depletion layer in these junctions widens with increase in voltage; the capacitance decreases. Thus we have a voltage- variable capacitance. Capacitances as high as 1 000 pF per mm : are possible through the use of lightly doped collector materials. A thin film capacitor can employ the n emitter area as the under plate, the silicon dioxide coating as the dielectric, and aluminum or other metallization as the upper plate of the capacitor. There will also be a stray capacitance to the p layer, in the reverse-biased isolating junction. The silicon dioxide capacitance can develop 300 pF*per mm 2 . Higher values can be made by use of tantalum oxide as the insulating film. In Fig. 10.24 we used the bulk resistivity of one of the diffused areas as a resistor. A thin film resistor can also be vapor deposited on the silicon dioxide insulating layer, using nichrome or tin oxide. The surface is given another layer of silicon dioxide for resistance protection. The resistance of thin films is given by K A Wy (10.50) where L is the length, W is the width, and y is the depth of the resistance stripe. If L = W or, for a square, «-f (£2 per square). (10.51) The resistance R, is called the sheet resistance and has units of ohms per square. In general, where L and W are not equal, we have *-*. W (10.52) Using material having R, = 100 Q per square, we can make a 2000 Q resistor of 0.025-mm width as L 2000 - 100 0.025 L = 0.025 x 2000 100 = 0.5 mm Resistances in the range from 40 to 400 Q per square arc possible. 266 Integrated Amplifiers 10.21 Comments The operational amplifier is probably the most widely employed electronic circuit device. Available in several hundred integrated circuit forms, it has many hundreds of applications of which we have indicated a very few. While we have discussed some of the basic circuits from which an integrated package is assembled, we are not normally much concerned with, and cannot even sec, the tiny internal circuitry. It is the gain and phase characteristics between input and output terminals that are important to us; as long as the internal gain is very high, we are not greatly concerned with that figure. But with gain controlled and stabilized with negative feedback, with high input resistance so that it takes negligible current from the driving circuits, with almost zero output resistance so that it can supply any reasonable output current, the operational amplifier in an integrated package is very nearly an ideal electronic device. That the basic idea of the integration of devices on a silicon chip need not be restricted to complex circuits has been shown by the Darlington and the cascode circuits. Simple differential amplifiers are also available as single units or with as many as four units on a single chip. REVIEW QUESTIONS 10.1 Why is the differential amplifier so well suited to integrated circuit production methods? 10.2 What conditions of equality make the differential amplifier operate as a balanced bridge? 10.3 What is meant by a differential signal? 10.4 What is meant by a common-mode signal? 10.5 What is ihe basic problem of amplification at dc or zero frequency? 10.6 What is the purpose of a single-ended differential amplifier? 10.7 Why is the differential amplifier circuit so well suited for dc amplification? 10.8 What is the common-mode rejection ratio? 10.9 Why is a large CMRR important in a differential amplifier? 10.10 Can we have a circuit with single-ended input and differential output? 10.11 What is the advantage of constant-current stabilization in a differential ampli- fier? 10.12 What is the action of the constant-current circuit when there is differential input to the amplifier? 10.13 What is the reason for the use of emitter follower circuits in integrated cir- cuits? 10.14 What is an operational amplifier? ■ Review Questions 267 10.15 Why do we use negative feedback in an operational amplifier? 10.16 What is the ideal gain of an operational amplifier? 10.17 What is an inverting amplifier? 10.18 What is the gain in a noninverting amplifier? 10.19 What is the ideal output resistance of an operational amplifier? 10.20 Why do we use voltage reference circuits in an op amp? 10.21 What is the function of a dc level shifter in an operational amplifier? 10.22 Does V,al the input of an operational amplifier actually equal V? Why not? 10.23 We sometimes say the input of a differential operational amplifier is at "vir- tual ground." What do we mean ? 10.24 What is the value of the input current to an operational amplifier, in an ideal situation? 10.25 What is the basic requirement in selecting an integrated amplifier for opera- tional amplifier use? 10.26 Can you explain why the CMRR is infinite if a truly constant-current source is used in place of R E ? 10.27 Sketch the transfer curve of a differential amplifier. 10.28 Draw an operational amplifier in block diagram form. Explain each func- tional block that you include. % 10.29 Define input offset voltage. 10.30 At what rate of gain fall versus frequency do we expect to find instability in the operational amplifier? 10.31 When we compensate an operational amplifier, what happens to the band- width? 10.32 What components do we use to frequency compensate an operational ampli- fier? 10.33 We wish to compensate an amplifier with an RC circuit having a corner fre- quency of 8500 Hz. We have a resistor of 25,000 £2; what C is needed? 10.34 What is a unity-gain isolator? 10.35 What is the purpose of an integrator? 10.36 Draw a circuit that would subtract two voltages, using an operational ampli- fier. 10.37 What is the slew rate? 10.38 Why are the frequency and peak voltage related in the slew rate? 10.39 In gain the Darlington connection is equivalent to what transistor circuit? What can you say about the relative input resistances? 10.40 Why do we use a Darlington connection at the input of a differential ampli- fier? 10.41 What are the advantages to be gained by use of a cascode circuit? 10.42 With what circuit is the voltage gain of a cascode equivalent? Integrated Amplifiers Problems 10.43 Why is the bandwidth of the first stage of a cascode circuit so large? 10.44 What is the expected bandwidth of the second stage of a cascode? 10.45 Name two methods of forming integrated circuit capacitors. 10.46 Name two methods of forming integrated circuit resistances. 10.47 What is the function of the SiO : layer in an integrated gain block ? PROBLEMS 10.1 The circuit in Fig. 10.2 has R L = 10,000 fi, R E = 3000 fi, R, = 1000 fi, hi, = 1500 fi, and h { , = 60. Find the differential input-differential output gain. 10.2 With h,, = 80, h„ - 1200 £2 in the circuit in Fig. 10.25(a), find the differ- ential voltage gain. - 15 V ww 1 + 15 V (a) (b) Figure 10.25 10.3 A differential amplifier has a differential gain of 150. To find the common- mode gain we determine that V, = 2 V, V = 20 mV when the inputs are in parallel. What is the CMRR value in decibels? 10.4 For a differential amplifier with R L 5000 fi, R E - 10,000 fi, R, = 2000 fi, h f , = 100, and g„ = 0.010 mho, find A«, A vc , and the CMRR value in decibels. 10.5 Find V„ for a differential amplifier with single-ended output and V,, — 0.55 mV, V,, = 0.40 mV, A« = 6000, and CMRR = 5 x 10*. 10.6 Find the output voltage of a noninverting operational amplifier for V, = 3.5 mV, R, m 40,000 fi, and R f - 240,000 CI, A = 50,000. 10.7 Find the output voltage for the circuit in Fig. 10.25(b), with V, = -4 V to ground, if R t =0.1 Mfi and R, = 0.5 MCI, if A v - 10 5 . 10.8 Find the output voltage for the circuit in Fig. 10.26(a), A = 10 4 . 10.9 Find the circuit gain in Fig. 10.25(b), with A = 10 4 , R, - 100 CI, and R, = 10,000 CI. 10.10 Find the noninverting gain in Fig. 10.10(b), with A = 10 4 , R, = 100 CI, and R f - 10,000 CI. Compare your result to that of Problem 10.10. 10.11 With R f = 500,000 Q, choose R, values and set up the circuit to obtain an output V„ = -iV„-6.SV b -AV C from three inputs V„ = 1 V, V b = 1.7 V, V, = 2 V. Hint: A unity-gain inver- ter might help. 10.12 Find the output voltage for the circuit in Fig. 10.26(b). with A large. 0.2 MSI - | Vo— WW — i 0.5 MSI + 2 Vo-^VWv 0.5 Mfi - I VC- 1 T. r 1 00.000 SI i 25.000 SI r (a) (b) Figure 10.26 10.13 Find V„ if V, = 1 mV in Fig. 10.25(b), gain A = 50,000, R, - 100,000 £2, and R f = 50,000 SI. 10.14 Find the output voltage for a three-input summing circuit with R f = 0.2 Mfi, R„ - 0.2 MCI, R„ - 0.35 MQ, R c - 0.45 Mfi. V, = -2 V, V b = 1 V, and V, = 3.2 V. 10.15 Determine the gain A,,, - VJV, for the circuit in Fig. 10.27(a), using A, (a) (b) Figure 10.27 260 Integrated Amplifiers = ^2 = 1 500. Remember that we can bisect the circuit into two circuits along the common line. 10.16 An operational amplifier has internal voltage gain of 80 dB, and at high fre- quencies the gain rolls off at a rate of —20 dB per decade. Unity gain (0 dB) is reached at 2 MHz; feedback ft - 0.03. What is the gain A' in decibels, and what is the corner frequency? 10.17 The/ 2 value of an operational amplifier occurs at 100 Hz and the no-feedback gain is 100 dB. What amount of feedback in decibels will be needed to reduce the gain to 40 dB, and what will the bandwidth become? 10.18 Assuming the transistors are not identical in the Darlington compound circuit in Fig. 10.27(b), show that /?/, S A t R E A, ~ Iif„h/„ Find A,. 10.19 Assuming the transistors of a Darlington pair, Fig. 10.27(b), are not identical, draw the circuit of an equivalent single transistor, and determine the h, and h f parameters in terms of h fe> , h ft „ h u „ and li lc ,. 11 Tuned and Video Amplifiers To select and amplify desired signals at radio frequencies we combine transis- tors or FETs with resonant circuits. Ideally wc would like to adjust those circuits to receive a narrow band of frequencies and reject all other frequencies but this is impossible at reasonable cost. So we define the selectivity of a radio receiver as a measure of its ability to separate a desired signal from other unwanted signals. In radio-frequency amplifiers we use a number of resonant circuits in cascade to raise the response to the desired band of signals and to reduce the response to unwanted signals near, but outside, the desired band. The transistor or FET isolates each resonant circuit and prevents the inter- action that would occur if these circuits were placed directly in parallel. The transistors also provide signal gain. Video amplifiers are designed with a frequency response extending from zero or near-zero frequency to 5 MHz or more for amplification of pulse signals. When designed with a response to 4.5 MHz, video amplifiers are used to amplify picture signals in television receivers. Transistors have gain fallofT in these frequency regions due to their inherent capacitance. We compensate the transistor circuits with inductance to extend the frequency range, again employing the principles of resonant circuits. 11.1 Bandpass Amplifiers In the radio-frecpiency amplifier, the usual input signal consists of a center frequency /„ around which are grouped a band of frequencies. The center 261 262 Tuned and Video Amplifiers frequency may range from one to many megahertz and the side frequencies may extend from a few to several hundred kilohertz on each side. Radio-frequency amplifiers are expected to provide selectivity for a desired frequency band and rejection of other frequencies. An ideal response curve is indicated by the dashed rectangle in Fig. 11.1(a). Ideally all fre- quencies in the desired band would be amplified equally and all frequencies outside the desired band, such as the interfering signal at/,, would produce zero response. We also require notability to shift the response rectangle over a wide range of frequencies at the will of the operator. Circuits must be simple since cascaded stages are simultaneously tuned and this requirement dictates that we depend primarily on the parallel-resonant LC circuit, with the capaci- tance element made variable for tuning. Such LC circuits provide only an approximation to the desired response rectangle and the discrimination against adjacent frequencies provided by the "skirt" portions of the curve is often inadequate. A measure of the relative selectivity is the shape factor of the response curve, as the ratio of the fre- quency width of the curve at 60 dB down from the center frequency response to the bandwidth at which a signal is only 6 dB down. For a single resonant circuit this shape factor may be 600 and, with 10- kHz bandwidth at 6 dB down from the resonant peak, the skirts cover 6 MHz for the 60-dB suppression. Several parallel-resonant circuits can be cascaded with their associated amplifiers to reduce the bandwidth at 60 dB suppression. Other amplifiers operate at intermediate frequencies (I.F.) between the radio signal frequencies and the audio frequencies. For example, the usual I.F. in a broadcast receiver is 455 kHz. Such I.F. amplifiers are tuned to fixed frequencies and greater circuit complexity can be tolerated since the ad- justments are usually made only by the manufacturer. These complex cir- cuits provide wider bands and steeper skirts on the selectivity curve, as shown in Fig. 11.1(b). (a) (b) Figure 11.1 (a) Narrow-band R.F. response; (b) response of an I.F. amplifier. The Parallel -Resonant Circuit 263 11.2 The Parallel-Resonant Circuit The parallel-resonant circuit in Fig. 11.2 is the common frequency-selective circuit in tuned amplifiers. The resistance R p is usually that of the source, as shown in Fig. 1 1.2(b), where a transistor drives a resonant circuit. We con- sider the scries resistance of the inductor and the capacitor as small. At resonance the voltage V is in phase with the current / and the circuit at A, A' appears as a resistance; this is the definition of the resonance condition. To bring this about, the reactance of the capacitance must equal the reactance of the inductance: and ih =lnf ° L (,U) at the resonant frequency/,, derived from Eq. 11.1 as 1 /■„ = (2n) 2 LC 1 (« 1.2) InjLC A parameter Q is defined as the ratio of the parallel resistance to either reactance at resonance so R, <> ~ if = ^Jl - 2 « f ° CR > c = R,J^- (11.3) (11.4) (a) (b) Figure 11.2 (a) Parallel-resonant LC circuit; (b) with a transistor. 264 Tuned and Video Amplifiers A resonant circuit should be efficient in transmitting power to the next transis- tor or load. The power lost in the circuit is y : /R p since C and L are assumed to provide no loss. With R p inversely proportional to the power lost, then Q is also inverse to the circuit losses. That is, a large Q indicates a low-loss circuit and we consider Q as a resonant circuit figure of merit;'" Q values ranging from about 5 to 500 are found in such circuits. The impedance of the parallel circuit at A, A' is Z = R. v'+^Gb At resonance, X c = X L and wc have Z = R P Using Eq. 1 1.3 this can also be written Z„ - 2nf LQ = 2nf C (11.5) (11.6) (11-7) Upon change of the frequency from the resonant frequency, either X c or X L increases and the difference term in the denominator of Eq. 11.5 be- comes larger and Z decreases. Since V Alt = IZ, the voltage falls as frequency departs from the peak value at R„, in Fig. 1 1.3. Driven by a transistor, the circuit provides a large voltage output at resonance and smaller voltages at all other frequencies. The phase angle of Z changes from inductive at frequencies below re- sonance to capacitive at frequencies above resonance. Equation 11.5 may be simplified for calculation purposes by rearrange- - O <t »«,= (a) (b) Figure 11.3 Equivalence of scries and parallel forms for resistance connections. '"When the circuit resistance is placed in scries with the inductance, the value of Q becomes The two equations for Q arc equivalent for the same circuit elements. Bandwidth of the Resonant Circuit ment. Consider the denominator difference term T c -Tr 2nfC ~WL -M"<**-=hd-m-f) (11.8) InfjLCl V L\f. f. after noting that 2n ^/LC — l/f . Inserting this result in Eq. 1 1.5, we have R. Z = We recognize that R P (C/L) = Q 2 from Eq. 11.4 and so have a simplified expression for the impedance Z = R, V' +«■(£-*)■ (11.9) In some cases, the resistance of the circuit is concentrated in series with the inductive branch, as in Fig. 1 1.3(a). For Q > 7, the series resistance R, can be transformed to a parallel R p , as », - r^ (11.10) R _ (2nf„LY ~RT or R R7~ (11.11) If a parallel resistance already is present, then the effective R„ is the parallel value of the two. The various equations for the parallel RLC circuit, such as Q and band- width and resonant resistance, can be applied after R, is transformed to an equivalent R p . 11.3 Bandwidth of the Resonant Circuit Figure II. 4 shows that the bandwidth of the resonant circuit, measured at the half-power points at which V = 0.707K„, depends on the value of R p . The exact nature of this dependence can be found by use of Eq. 1 1.9. Wc previously showed that the frequency of a bandwidth limit was found when the two terms of the denominator of an expression such as Eq. 1 1.9 were equal. Thus at the upper frequency limit/,, identified in Fig. 1 1.4, wc have .-<!■(£ -4) 266 Tuned and Video Amplifiers 10 9 -r p = io.ooo n 8 V 7 '.W (l 2 6 o > 1 5 / / -R p ■ 5000 n_ & 4 7 / Blf 3 2 1 950 975 1000 Kilohertz 1025 1050 Figure 11.4 Resonance curves for two R p , L, C parallel circuits. Taking the square root. The lower limit at/, is below/, and the term in parentheses must be reversed to remain positive. After taking the square root, If/ 2 and/, are small departures from/,, then we can say that £i_f.~ 2(A-/o) (11.12) Suppose that/ 2 = I.I/,; then 1.0 1.1 u.yi = u.z_ j Bandwidth of the Resonant Circuit and the approximation is reasonable. Therefore, we have ■=M¥) » /, 267 (11.13) (11.14) Adding these expressions, we have /a-/, The bandwidth (BW) as/ 2 -/, is «P=/*-/,=^ (Hz) (11.15) This expression again defines Q and while instruments for measurement of Q are available, the value of circuit Q is often calculated from a mea- surement of the bandwidth of a circuit while it is mounted in the equipment. That is, /, and / 2 are measured where the voltage response is VJ^fT, and Eq. 1 1.15 is used to find Q. High Q and low losses are indicative of narrow bandwidth and large R„. By variation of the resistance R„ connected across the circuit, we can adjust Q and the bandwidth. Equation 1 1.4, shows that the C/L ratio of a circuit also controls Q, that is, a large ratio of C to L gives a high Q circuit. At the bandwidth limit frequencies the phase angle of Z is 45° below resonance and —45° above resonance at f % . Example: Choose L and C values for resonance at 1 MHz, with a reso- nant impedance of 100,000 Q. and bandwidth of 10 kHz. We then have Z„ = R„ = 100,000 £1 Also Z„ = 2nfJjQ = R 100,000 6.28 x I0 6 x 100 - 159 /zH = 0.000159 H 268 Tuned and Video Amplifiers We also have Q - 2nf.CR, C = Q 100 2nf.lt, " 6.28 x 10 s x 10 s = 159 pF = 1.59 x 10-'° F 11.4 The Single-Tuned Transistor Amplifier We frequently use a resonant circuit for both coupling and selectivity between two transistors, as in Fig. 1 1. 5. The load on the resonant circuit at 2,2 is the input resistance of transistor Q 2 , usually increased over h lt by use of an unbypassed emitter resistor. Figure 11.5 Single-tuned, inductively coupled circuit. The secondary voltage V B , will be maximum when the circuit is tuned to resonance and I = 2nf.Lt (11.16) WJCt With M as the mutual inductance between the coils I, and L 2 , we choose 2nf.M - ~/R^R7, (11.17) We find that the secondary voltage at resonance is (11.18) where our effective circuit Q, value relates to the circuit Q 2 of the secondary tuned circuit as Mi Q.= 1 + (W.M) 1 (11.19) The Double -Tuned Transformer Using the condition of Eq. 11.17, 269 and the bandwidth is 0.-<b ""-£-£ (11.20) which, with optimum M from Eq. 11.17, is twice the bandwidth of the secon- dary resonant circuit alone. By reducing M from the optimum value, we can control the bandwidth from twice the Q 2 value to that of Q 2 . The transformer should have the approximate relation = /Ru^n, V R n ~ n 2 (11.21) where n,/n 2 is the ratio of primary to secondary turns. This is only an ap- proximate relation for such radio-frequency transformers, dependent on the completeness of the iron core surrounding the coils. 11.5 The Double-Tuned Transformer For use in intermediate frequency amplifiers, where tuning is fixed by the manufacturer, we can widen and square up the response curve still further by tuning both primary and secondary windings of a transformer, as in Fig. 11.6. Usually we make L, — L 2 and Q, = Q 2 = Q; both sides of the trans- former will also be independently resonant at/,. The magnetic coupling between L, and L 2 is measured by the coefficient of coupling k. With the coils far apart, k — and the secondary voltage is low. As the coils are moved closer together, the secondary voltage rises to a maximum at the value of critical coupling at k = k c in Fig. 1 1.6(b). As the coils are moved still closer, the secondary voltage falls again. The critical coupling value of A: is k c = -^== (11.22) and for Q t = Q 2 = Q we have V0.0* k. = -k (11.23) The circuits are said to be undercoupled if k < k c , critically coupled if k = k e , and overcoupled if k > k c . When we plot secondary voltage against frequency, and the value of k < k c , we have response curves with one peak, as shown for kjk c -= 0.5 in Fig. 1 1 .6(c). The secondary voltage V., reaches a maximum peak value for k/k c = 1. This is equivalent to k = \/Q. Because of interactions between 270 Tuned and Video Amplifiers k/k c =kQ = 2.Q Figure 11.6 The doublc-tuncd circuit. the currents in the two resonant circuits when k/k c > l,k > l/Q, the res- ponse curve splits and shows two frequencies of maximum response and the bandwidth widens. The frequencies of peak response are I (11.24) (11.25) At critical coupling, with A: = l/Q, the expressions indicate that /„ =/» — /„ for the single peak, as they should. If the dip in the center is allowed to fall to 0.707K pe , k , the bandwidth is The gain at either frequency of peak response is M.. t | = 27t/ °^ gL; (11.26) with L, = L t . Such transformers cannot simply be aligned by tuning for a peak secon- dary voltage with overcoupling. One procedure is to reduce the Q value, thereby changing the coupling from overcoupled to undcrcoupled. This is The Pulse Waveform 271 done by shunting fixed resistors on both primary and secondary. If k — 0.05 and Q, — Qi = Q = 50, then k t — 0.02 and the transformer is overcoupled. If we reduce Q to 15, then k c = 0.067 and the transformer becomes under- coupled and gives only one response peak. Tuning for this peak will correctly establish both primary and secondary resonance. The loading resistors can then be removed. The use of two tuned circuits produces a response over a greater band- width and with steeper skirts on the response curve so that the response more nearly approaches the ideal rectangle. More elaborate circuits are available with greater numbers of tuned circuits. Each circuit adds a small ripple of gain to the passband response but steepens the falloff at skirt fre- quencies. These are known as stagger-tuned amplifiers. The analysis is beyond the scope of this text. 11.6 The Pulse Waveform In digital computation, data transmission, and radar we use the pulse wave- form, shown in ideal form in Fig. 1 1.7(a). After transmission through various circuits and amplifiers, the waveform may appear more as in Fig. 1 1.7(b) or (c). The pulse starts at / — but the received pulse is delayed by the transmis- sion path as in Fig. 1 1.7(b). The exact starting time involves guessing as to when the received wave leaves the zero axis; to avoid this uncertainty the rise time of the pulse is arbitrarily defined as /„ from 10 to 90 per cent ampli- tude. The pulse width is also difficult to determine so it is defined as t w , mea- sured between the 50 per cent rising level and the 50 per cent falling level. The top of the pulse may sag some percentage d or may overshoot by some percentage of the amplitude as shown in Fig. 1 1.7(c). One of the major needs for the video amplifier arises in the amplification of pulses because of the large bandwidth needed for good waveform repro- duction. A general pulse train, as used in data transmission, is shown in Fig. (a) (b) (O Figure 11.7 Pulse waveforms. 272 Tuned and Video Amplifiers m Figure 11.8 A pulse train. 1 1.8. Each pulse is At seconds long and the pulses are repeated at a repetition rate off R = \/T R per second. Each pulse is made up of an infinite number of harmonic frequencies, starting with the fundamental or first harmonic at f R , a second harmonic at 2f R , and more harmonics at nf R frequencies to in- finity. Of course, the very high-order harmonics are small in amplitude and are cut off by the amplifiers since no amplifier can have a passband to infinite frequency. But the fidelity of the pulse waveform is dependent on the video amplifier's providing a uniform gain passband for these harmonics. Excellent reprpduc- tion is possible if the passband is wide enough to amplify frequencies to ^ rfs fh) Figure 11.9 Approximaiion lo a square wave: (a) fundamental frequency; (b) fundamental plus third harmonic; (c) fundamental plus third and fifth harmonics. The Shunt-Peaked Video Amplifier 273 4/Af, and reasonable reproduction is obtained with a passband reaching to |/A/ hertz. Thus for a l-/is pulse equal to At, repeated 400 times per second, the bandwidth for excellent reproduction would be 4 MHz and for reasonable reproduction we would need a 1-MHz bandwidth. In that 4-MHz passband there are harmonic signals every 400 Hz, or 10,000 signals must be amplified equally. The process of building a wave through addition of the harmonic fre- quencies is shown in Fig. 1 1 .9. Very high-order harmonics arc needed to build the square corners. The harmonic amplitudes that are needed for the first few frequencies of a square wave are given in Table 11.1. TABLE 11.1 Relative Amplitudes of Harmonics in a Square Wave* Harmonic Amplitude Harmonic Amplitude Harmonic Amplitude 1 0.636 II -0.058 45 0.014 3 -0.212 13 0.049 55 -0.011 5 0.127 15 -0.042 65 0.0098 7 0.091 25 0.025 75 -0.0085 9 0.070 35 -0.018 85 0.0075 •Wave amplitude -- 1. Negative signs indicate reversed phase. 11.7 The Shunt-Peaked Video Amplifier The video amplifier has been defined as having a frequency range extending from near zero to a few megahertz. This takes the operating range into the frequencies at which the Miller-effect capacitance of the transistor or FET normally produces a fall in gain. One way to widen the frequency response band of an amplifier is to reduce the load resistance. This reduces the gain and the Miller-effect capacitance and raises the/. limit of the amplifier. The/ 2 limit may be further raised by use of an inductance in the load. The resulting resonant effect raises the load impedance at those frequencies where C,,, in shunt, reduces the load. The gain is maintained uniform to a higher/ 2 value. In Fig. I l.lO we show the compensating inductance L, usually a fraction of a millihenry, connected in series with the FET load resistor R,. In Fig. 1 1. 10(b) we have the equivalent circuit of the transistor, including the Miller- effect capacitance of Q 2 and the wiring capacitance, which together form C T . We have neglected and dropped the series blocking capacitor and the bias network from the circuit. With L = we have an uncompensated amplifier with load R, and the 274 Tuned and Video Amplifiers <?+ V. lo- «fe lo- ftl _£. <■< :« 2 K,, " 6+l',r- *+«'«■ (a) r- ^ a: - (b) Figure 11.10 (a) Shunt compensation by L; (b) equivalent circuit. upper limit frequency is h = I SCT <"- 27 > obtained by the methods of Chapter 8. We use this frequency as a norm, against which the higher/', of the compensated amplifier will be compared. The circuit is said to be shunt-compensated by the inductance. We define a parameter as _ 2nhL L H R, R;C T (11.28) after using Eq. 1 1.27. This equation expresses the ratio of inductive reactance at the/ 2 frequency to the series resistance. The inductance L is then varied and frequency-response curves plotted as in Fig. 11.11. The curve fore/ m is for the uncompensated amplifier with L = 0. The condition of q = 0.41 is found to give the widest frequency band without a rise of gain above the mid-range value and for that value of q the bandwidth is increased to/i = 1.72/. The Shunt-Peaked Video Amplifier + 5 275 33 -5 . io a 0, 1 "^ ).s\ ti^^^X :odB it Decat - p k- 1 = y I r 0.1 0.2 0.S I 2 5 Mi Figure 11.11 Shunt-peaked circuit response versus parameter </. Values of q > 0.41 widen the response band further but introduce a peak at some frequency less than/ 2 . It should be noted that while one stage may show a peak of G decibel, n stages will increase that peak to nG decibels and such a high peak may not be acceptable. We can find the time delay in transmitting a frequency through the am- plifier from the phase angle 6. Using 0/360 as the fraction of a cycle by which the signal is delayed and l//as the time of a cycle, we can write 9 time delay — 360/ Figure 1 1 . 1 2 is plotted in terms of time delay. If all frequencies are given an equal time delay, the curve will be flat and the whole wave will be delayed 0.16 0.1 0.2 0.5 1.0 2 5 Mi Figure 11.12 Time delay for the shunt-peaked amplifier. 276 Tuned and Video Amplifiers The Series-Peeked Video Amplifier 277 but is unchanged in waveform. Therefore, q = 0.32 offers the best phase response. A compromise between q ^ 0.41 and q = 0.32 is often made at about q = 0.35. With </ = 0.35 and R, chosen for suitable low-frequency gain and band- width/,, we can find the value for the compensating inductance from Eq 11.28: L = qR)C T (11.29) The high-frequency gain of the compensated amplifier is given by a com- plicated expression: /U " = - g "4 i-Hi-w(^ g W 2 )J 2 (,, - 30) where — g m R, is the mid-range gain. The phase angle expression is also com- plicated: 0- -tair'£[l -q+q^L^ (11.31) The rise in gain at the high frequencies is due to resonance between L and C T , the lower peaks being produced as a result of a low value of circuit Example: An FET has g„ = 0.003 mho and is to be used in an amplifier to provide a mid-frequency gain of 10, with the gain extended to the highest possible frequency. The FET has C, , = 1 pF and C, d = 2 pF. We find R t from the mid-frequency gain: ^.(midi -' —g m R, = 10 10 K.= (1.003 = 3300Q The Miller-effect capacitance is C„ = C„ + (1 + g m R,)C, d = 1 + (1 - 0.003 X 3.3 X 10 3 ) X 2 = 1 + 22 = 23 pF We then add 2 pF for wiring capacitance so that C T — 25 pF. The limit frequency of the uncompensated amplifier is 1 1 h- 2nC T R, In X 25 x 10"' 2 x 3.3 x 10 J = 1.93 MHz By use of L = qR)C T = 0.41(3.3 x 10 3 ) 2 x 25 x 10" l2 = 1.12 x 10-«H-=0.112mH we can extend the frequency range to f\ = l.72/ 2 = 1.72 X 1.93 = 3.32 MHz 11.8 The Series-Peaked Video Amplifier A more elaborate circuit that also raises the high-frequency response limit is the series-peaked circuit in Fig. 11.13. We add a small inductance in series with C r , with which it resonates to raise the gain at the high frequencies. For the uncompensated amplifier with L -— 0, the mid-frequency gain is A c , mU , - -g m R, (H-32) and the/ ; frequency limit is 1 A- (11.33) 2s(C, i C T )R, where C, is the output and wiring capacitances of the first transistor Q t . The optimally flat response is obtained when and q = MlL =, 0.67 R, c, -^ giving a bandwidth of/i =- 2/ 2 . Using Eq. 1 1.33 in 1 1.34, we have L = A = qRKC, ■■ C T ) InJz (11.34) (11.35) (11.36) Often the output capacitance of Q, is not exactly one-third of C T , as called for in Eq. 1 1.35. To increase either C, or C T to obtain this ratio will reduce /, as calculated by Eq. 1 1.33. But a reduction in f 2 is not the result desired. Accordingly, the shunt-peaked circuit, with its lessened complexity, is gen- erally used in video amplifiers. -It- -CI + v, cc Figure 11.13 The serics-pcaked circuit. 278 Tuned and Video Amplifiers 'ova *u (mid) 1.2 1.0 0.8 0.6 0.4 0.2 C^ k K ^ ^ 0.1 0.2 0.5 10 Ml Figure 11.14 Comparison of shunt and scries compensation. A comparison of the uncompensated and compensated responses is made in Fig. 11.14. 11.9 Review Q is a most important and useful parameter of the parallel-resonant circuit. It is defined as where i InJLC for the circuit-resonant frequency. We then know that the bandwidth is «r -/»-/.-<§ and that at resonance Z « R, = 2nf LQ For frequencies near resonance, R, Z = V'^tt-i)" For the tuned coupled circuit the bandwidth can be increased to 2/JQ with critical coupling k c for the coils and cuM equal to As /R i ,/?,,. Further Review Questions 279 widening and steepening of the skirts is possible by tuning of both primary and secondary and making k > k c . These methods lead to a response that is closer to the ideal rectangular shape for the response curve. The shunt-compensated circuit is most usually employed in video am- plifiers. REVIEW QUESTIONS 11.1 Define resonance. 11.2 Why do we desire a rectangular frequency-response curve? 11.3 What is the condition of the circuit reactances at resonance? 11.4 What is the resonant frequency? 11.5 Define selectivity. 11.6 What is the shape factor of a resonant circuit? 11.7 What range of bandwidths do we expect to find in radio-frequency amplifiers? 11.8 How is Q defined in terms of circuit elements? 11.9 How is Q defined in terms of bandwidth? 11.10 How do we often measure Q1 11.11 What is the resonant resistance of a parallel circuit? 11.12 Why is the resonant resistance a maximum at resonance? What happens to the currents in L and C? 11.13 What is the bandwidth of a resonant circuit? 11.14 A circuit has a resonant frequency of 100 MHz and a bandwidth of 5 MHz. What is the Q1 11.15 A circuit has a shape factor of 100: I and is 6 kHz wide at 6 dB down from the peak. What is the width of the curve at 60 dB down? 11.16 What are the phase angles of the resonant impedance at the bandwidth limit frequencies? 11.17 How does the C/L ratio affect the bandwidth? 11.18 What is the tuning result of (a) Critical coupling? (b) Overcoupling? (c) Insufficient coupling? 11.19 In a tuned coupled circuit, on what factors does V„, depend? 11.20 On what factors docs the bandwidth depend in a tuned coupled circuit? 11.21 What is the maximum value of the coupled Q, in terms of the circuit Ql 11.22 Define critical coupling in terms of Q. 11.23 What is a video amplifier? 11.24 How do we shunt compensate a video amplifier? 280 Tuned and Video Amplifiers 11.25 How do we scries compensate a video amplifier? 11.26 Why do we avoid a gain peak in a cascaded shunl-compensated amplifier? 11.27 What is the parameter q in a shunl-compcnsated amplifier? 11.28 What is a good compromise value for q in a shunt-peaked amplifier? 11.29 What is the requirement on the two capacitances in a series-peaked amplifier? 11.30 How would you tune a double tuned overcoupled transformer? 11.31 In a parallel-resonant circuit, in order to make the circuit inductive, should the generator frequency be raised or lowered from resonance ? 11.32 To raise the resonant frequency of a parallel circuit, which is it necessary to do? (a) Increase the capacitance (b) Increase the resistance (c) Decrease the inductance (d) Increase the inductance 11.33 What is the repetition rate? 11.34 How is pulse rise time measured? 1135 How is received pulse width measured? 11.36 What is overshoot of a pulse? 11.37 How many harmonics are in a pulse wave? 11.38 How many harmonic frequencies are needed for excellent reproduction of a pulse wave with repetition rate of 1000 per second, at 10-MHz frequency? PROBLEMS 11.1 A circuit is resonant at 2000 Hz. If the coil is 0.120 H, what capacitance is being used ? 11.2 A parallel circuit is resonant at 5.35 MHz and uses a 40-pF capacitor. What is the value of the inductance? 11.3 In a parallel-resonant circuit the reactance of the capacitance is 1450 Q and R p = 20,000 Q. What is the Q of the circuit? 11.4 In Problem 11.3, the inductance is 250 fiH. What is the frequency of reso- nance? 11.5 At resonance in the circuit in Fig. 1 1.15(a), / = 10 mA and V - 7.5 V. What is the resonant resistance of the circuit ? 11.6 In Problem 11.5 the inductive reactance at resonance is 455 Q. 2nf L; what is the value of Q ? 11.7 Capacitor C in Fig. 11.15(a) is 350 pF. Using data from Problems 11.5 and 1 1.6, what is the resonant frequency? 11.8 The half-power points of the frequency response of a resonant circuit are 647.5 and 662.5 kHz. Problems 281 (a) (b) Figure 11.15 (a) What is the resonant frequency? (b) What is the circuit Q? 11.9 A parallel-resonant circuit as in Fig. 11.15(a) has Q = 150 and / = 0.6 mA. The voltage Vh 100 V. (a) Find the reactance of L and C at resonance. (b) What power is being supplied to the circuit? 11.10 Using the circuit in Fig. 11.15(a), the voltage V is 55 V; R p =4500£2, L = 5 fiH, and C - 0.001 //F. (a) What is the resonant frequency? (b) What is the circuit Q1 (c) What is the current / at resonance? 11.11 A parallel RLC circuit is resonant at 27 kHz. The circuit contains a 0.015-H inductance, a 0.002316-//F capacitor, and a parallel resistance of 40,000 Q. (a) What is the circuit impedance at resonance? (b) What is the circuit Qt (c) What is the bandwidth? (d) What is the circuit impedance at / ; ? 11.12 The circuit in Fig. 11.15(b) is to tune the broadcast band from 550 to 1600 kHz. The capacitor is varied and has a maximum value of 375 pF. What is the value of inductance used, and what should be the minimum value of C? 11.13 A circuit is resonant at 455 kHz and has a 10-kHz bandwidth. The reactance of the inductance is 1250 Q; what is R p of the circuit? 1 1.14 A parallel-resonant circuit is resonant at 20 MHz, the Q is 1 50, and the react- ances are each 750 Q. What is the value of R p and of an R, in series with L that might replace R p l 11.15 In a parallel-tuned circuit, the resistance in series with the inductor is 12 Q and the inductive reactance is 1450 Q at resonance. Find the Q of the circuit. 11.16 The resonant frequency of a parallel RLC circuit is 7.3 MHz. If the Q is 80, find the half-power frequencies. 11.17 A parallel RLC circuit is resonant at 20 MHz. The Q is 200 and the reactances are 750 £2. (a) What is R p 1 (b) What resistor should be paralleled with R p lo bring the Q down to 50? (c) What are the bandwidths, with and without this resistor? 282 Tuned and Video Amplifiers 11.18 In a resonant circuit, C = 60 pF and L is 1 30 ^H. The Q of the circuit is 150 and R p = 100,000 Q. What is the bandwidth in hertz? 11.19 A parallel circuit is resonant at 2 MHz. In order to have the circuit resonate at 10 MHz, what must be the ratio of the new capacitance to the original capacitance? 11.20 The circuit in Fig. 1 1.3(a) has L = 0.01 H, C = I ^F, and R, = 3 Q. Deter- mine /„, BW, and Q. 11.21 Two circuits of the type of Problem 1 1.18 are critically coupled. Determine k c . 11.22 In a double-tuned circuit, k - 2k c and Q - 80. If/, = 10.7 MHz, (a) What are the frequencies of peak response? (b) What is the circuit bandwidth if the gain is down 3 dB at the dip at/,? 11.23 A double-tuned transformer has L, = L 2 = 100 [M, Q, = Q 2 = 100, with coupling k at 150 percent of critical. The source hasg m = 4500 //mhos. (a) Find the values for C, and C 2 for resonance at 1.59 MHz. (b) Compute the frequency separation of/ and/. (c) What is the voltage gain at resonance? 11.24 An FET amplifier is to have a gain of 20, extending to the highest possible frequency. Find that frequency when shunt-compensated, with q = 0.41. Also find L needed if g m = 0.0025 mho, C„ - I pF, C gi = 2.5 pF, wiring capacitance = 3 pF. 11.25 A shunt-peaked video amplifier uses an FET with g m 0.0025 mho, C, d = 2 pF, C„ - 1.5 pF, C» = 2 pF, and R, = 4000 fi. When designed for q = 0.41 find the/; frequency and the needed value of L. What is the low- frequency gain? 11.26 A pulse chain of0.5-//s pulses is sent at a rate of 4000 per second. What ampli- fier bandwidth will be needed for reasonable pulse wave form at the output? For excellent wave form ? 12 Power Amplifiers We now wanl to put our signals to work, and large power outputs are required for such purposes as driving loudspeakers or scrvomechanisms or transmit- ting radio signals through space. Amplifiers providing large power outputs require large input signals. The small-signal equivalent circuit cannot be used and we must go back to the graphical method of transistor or tube analysis. Since the output curves are not linear for large-signal excursions, we have to determine the output wave distortion and devise circuits for reducing that distortion. For maximum power output the loads should match the output resis- tances of the amplifiers. Direct matching of output resistance and load does not always happen. More usually we have to use an impedance-transforming circuit or transformer to supply the matched load conditions necessary for maximum power transfer. Therefore, in our analysis of power amplifiers we shall be interested in such items as distortion levels, power efficiency of the transistor, elimination of the heat losses, and the impedance-matching circuits. 12. 1 Defined Operating Conditions Three broad areas of operating conditions are defined for power amplifiers, dependent on the chosen bias and the input voltage amplitude. We use the letters A, B, and C to designate these conditions, as demonstrated for a tran- sistor in Fig. 12.1. 283 284 Power Amplifiers Class A Class B (a) <l» Class C (O Figure 12. 1 Transistor operating conditions. For Class A operation, the bias is .selected to place the Q point near the center of the transfer curve relating v Be and i c . Collector current is present for all values of signal input, as shown. This is the operating condition of the small-signal amplifiers in our preceding discussions. Distortion is low but the power output is also low because of the small input signal. The effi- ciency of conversion of dc power to ac power is limited to 50 per cent. Prac- tical transistor amplifiers can reach 45 per cent. With Class B conditions, the bias is selected to place the Q point on the cutoff line and collector current is present only on the forward half cycle of the input voltage. During the reverse half cycle, collector currcnf is not present in the output of the transistor. Distortion is therefore high but the efficiency of power conversion can reach a theoretical maximum of 78.5 per cent. Push-pull circuits are employed to supply the missing half cycle and to reduce the distortion to usable levels. Practical efficiencies reach 65 per cent. For operation in Class C, the bias is set to two or more times the cutoff level and current occurs only in short pulses near the forward peak of the input wave. Theoretical efficiency reaches 100 per cent but the distortion is so high as to limit the circuit's application to radio frequencies where the distortion harmonics can be filtered out by resonant circuits. Practical efficiencies reach 80 per cent. Transistor power amplifiers employ the C-E circuit because of its high power gain; similarly, tube power amplifiers use the grounded-cathode cir- The Ideal Transformer 285 cuil. Class A and B conditions yield amplifiers suited to audio-frequency power amplification and Class B and C amplifiers are used at radio frequen- cies. Because of the special methods required for the analysis of Class C amplifiers with current pulses of varying length and because of their limited application, the Class C amplifier svill not be discussed here. 12.2 The Ideal Transformer The transformer in Fig. 1 2.2, with a laminated iron magnetic core, is often used as an impedance-transforming device in amplifiers operating at audio frequencies from 50 to 1 5,000 Hz. Iron Core Figure 12.2 The ideal transformer. The transformer is efficient in handling power. The voltages and currents present in the primary and secondary are related by the turns ratio a — giving the voltage and current ratios as The secondary load is On the primary side of the transformer we have But from Eq. 12.2 we can write *,=$ ii *' -77 (12.1) (12.2) (12.3) (12.4) and inserting these values into Eq. 12.4 we have R . .eV % _ .V* R >-7Ja- a h 286 Power Amplifiers But K 2 // 2 - R, by Eq. 12.3 so *i = « 2 *: (12.5) A load in the secondary appears in the primary as a resistance a 2 R 2 , with ac voltage applied. We say "appears" because /?, is present only when alter- nating voltages are present; a direct current does not affect a transformer. Thus a loudspeaker of 4 ft can be made to appear as 400 ft on the pri- mary side if we use a transformer with the turns ratio fl =, yi|° _ yroo - 10 Such an impedance-transforming device is called an ideal transformer. Actual transformers closely approach the ideal transformer performance. The transformer also isolates the dc component of collector current from the load. For dc the transformer primary appears as the low dc resistance of the primary winding, often considered to be zero. 12.3 Power Relations in the Class A Amplifier For the large-signal amplifier with an output-matching transformer and under Class A conditions, the circuit is that in Fig. 1 2.3. Calculation of performance must be derived from the 'graphical output characteristics because of the nonlinearity of the transistor curves for large-signal excur- sions. To obtain large power output we operate the transistor with large power input and the internally developed heat is the limiting factor. The input power is obtained from ihe collector supply and partially converted to signal Figure 12.3 The C-E power amplifier. power Relations in Ihe Class A Amplifier 287 (12.6) output power and delivered to R„ through the transformer. We have power input =» ac output | losses YcJc = Wi + {VceIc + /^dc) where R ic is the dc resistance in the collector circuit, outside the transistor, V CB l c being the steady transistor loss at the Q point. Equation 12.6 shows that the transistor loss or dissipation is P* - VceIc = V cc l c - l c R ie - J 2 R, (12.7) The signal output term is /*/?, and as it increases, the transistor loss K C£ / C must decrease and the transistor operates cooler in Class A. We must design for the worst possible case of no signal, however, so we have the £-point loss as max />< = V cc l c - I c R ie (12.8) The primary winding of the transformer usually has negligible dc resistance and in most amplifiers ft* = Ra (12.9) as the value of the emitter bias resistor. Resistance R E is also kept small, however, since its resistance reduces the overall power efficiency and we shall neglect it in this somewhat idealized case. Therefore, max P d - Vcclc - I C R E = V cc l c (12.10) and this establishes the expected transistor loss in the circuit. The limiting hyperbola in Fig. 12.4 is drawn for an allowable transistor loss at a specified operating temperature; it may be less than the indicated AC Load Line "mm Figure 12.4 Construction of the ac load line. Power Amplifiers loss from Eq. 12.10 and selection of that allowable loss is a thermal problem that will be discussed shortly. The Q point will be located on or below the limiting dissipation curve. The presence of the transformer introduces a new step in the construc- tion of the load line since with a transformer the dc and ac loads are not the same in resistance. We first select a V cc , usually one-half the maximum rated collector-emitter voltage V CElmtx) . We then draw the dc load line, which always starts at V cc . Since the dc resistance of the collector circuit in Fig 12.3 is assumed zero, the slope will be - l//? de = -1/0, and the dc load line will be vertical as shown dashed in Fig. 12.4. The intersection with the locus will establish the Q point. The presence of R E would have given the dc load a slight slope to the left but would not alter the general situation. This is discussed in the example that follows. Draw the ac load line from 2V CC on the x axis and through the Q point. The y intercept of the ac load line establishes / mtI and the slope of the line is that of R„ which is the primary load to be supplied by the transformer. That is, from the slope /?,= 2V, cc _ Ycc lc (12.11) since / ra „ = 2/ c by the geometry of the figure. The power loss is P t — V rc l c and we can also write The base current will be driven symmetrically to some values at I B , and I B , as shown, and the transistor will reach peak collector currents as i mtx and /„,,„. The power output is found from these peak values of a sine wave as ~~ 8 (12.13) From the figure / c - (/„,„ - i m J/2 and the efficiency of conversion of the dc power to signal power is eff. - £ x 100% - {'mil <mln)°l 4r, cc X 100% (12.14) The efficiency depends on the amplitude of the output signal. For the greatest possible output signal that swings over the complete length of the load line, we have / ra!n = and 2y cc /R, = i mp Then eff. = -0 = 4^ = 50% 4K CC //?, " 2i m „ and this is the maximum theoretical power conversion efficiency for the transformer-coupled Class A amplifier. (12.12) I B , and as / Power Relations in the Class A Amplifier 289 The saturation voltage limits /„,, to values less than the theoretical but because of the low saturation voltage of most transistors a practical amplifier can approach the theoretical figure. Vacuum tubes, with much higher satura- tion voltages, rarely exceed 30 per cent in conversion efficiency. Example: Select a load and determine the power output and conversion efficiency for a signal i„ == ±60 mA, maximum possible, applied to the tran- sistor in Fig. 12.5. It is rated Fcflfiux) = 65 v > p * aB 30 w un der the expected operating conditions and with R B = 1 Q. We first draw the maximum-power dissipation curve for 30 W as shown and select V cc = f^£ = ** = 32.5 V A bias resistor R E = I £2 and so the dc load line is drawn with a — 1/1 slope to 1 A and 32.5 - I = 31.5 V. The Q point is then found at I c = 0.94 A. The ac load line is drawn from 2V CC — 65 V through the Q point and ^, c is found from the slope as R — ^ CE — — 34 Q but R, = R, e — R E — 34 — 1 = 33 £2. We need a transformer to transform 20 Vcc 4° fi0 v CE (V) Figure 12.5 AC load line. 290 Power Amplifiers R, = 4 Q of a loudspeaker to 33 €1. The turns ratio must be «-Vf-2. 8 7 With the designated input base signal we swing along the ac load line up to i„ m> 120 m A and down to i B = 0, giving / m „ = 1.70 A and f„„ = 0.05 A. The power output is , t JLW-Myx33 ta „ 2W The power input to the circuit is />,„ = 32.5 x 0.94 = 30 W as expected and the power conversion efficiency is efT. -^x 100 = 37% 12.4 Voltage Limitations The manufacturer specifies a maximum safe value for V cz but the transistor has some physical limitations on the voltage that may be applied. The collector-base depletion layer widens as the collector voltage is increased and the depletion layer may extend completely through the thin base region at some high voltage. This is known -as punch-through. The transistor under this condition appears to have a short circuit between emitter and collector. The base loses control until the collector voltage is reduced. Avalanching of charges may occur in the collector region at a high voltage; however, no physical damage results. This is known as first breakdown. If the avalanching current channels into small areas, a hole may be melted through the base. This is known as second breakdown and the transistor is destroyed. The maximum voltage for vacuum tubes is determined by the insulation limits and is specified by the manufacturer. 72.5 Effect of the Thermal Environment In order to keep the collector-base junction leakage current small in compari- son to the signal current in the collector, it is necessary to keep the temperature of the junction below 200°C (392°F) for silicon transistors and I00°C (2I2°F) for germanium transistors. The rate of heat removal from the collector junction is proportional to the difference in temperature between the collector and the ambient sur- Etfecl otthe Thermal Environment 291 roundings of the transistor. With 7', as the junction temperature and T A as the ambient temperature in °C, T 3 T A = d ]A P d (12.15) where JA is the thermal resistance of the transistor case and mounting in units of °C/W. The thermal resistance really states the temperature differential needed per watt of heat removed from the transistor. The power level for which the dissipation curve of a transistor is drawn is dependent on the thermal resistance of the transistor case and its mounting and on the ambient temperature surrounding the equipment. In small-signal amplifiers, P d is usually at milliwatt level and air convection and conduction by the transistor leads is sufficient to remove the generated heat. For higher- power amplifiers the transistor mounting is designed to dissipate the heat by metallic conduction and convection by the air or by forced-air cooling. The collector junction is usually in good thermal contact with the case. Electrical insulation is obtained by mounting on a base plate with a thin mica insulator with the air pockets filled with silicone grease. The base plate may be fitted with convection fins and is then known as a heat sink. This improves the heat transfer to the air. But even the heat sink is not able to reduce the case temperature to that of the surrounding air and the junction temperature will be above that of the case. The air may be considerably above 25°C as well. The characteristics of a small heat sink arc given in Fig. 12.6, with Oca = 3°C/W. Suppose that we have a transistor in which 6-VV dissipation produces the junction limit temperature when the case is Held at 25°C in a water bath. But in air at 25°C the case temperature will be much above 25°C because of the Aluminum Fins Transistor ,n n n n n/n n n .§ 60 .c £ < o -C. 4(1 -r\— BE -10 cm 1 2.5 cm S r cc 1 20 o. E f- 10 20 30 Watts in Free Air (a) m Figure 12.6 (a) Finned heal sink and transistor, MS-10; (b) temperature rise, thermal resistance ■> 3°C/W. 292 Power Amplifiers poor heat transfer from case to air. The junction temperature must rise by the amount the case temperature exceeds 25°C in order to continue to conduct 6 W from the junction. Therefore, with a higher temperature for its sur- roundings, we must derate the allowable transistor power level. This is con- firmed if we write Eq. 1 2. 1 5 as Tj = 6 JA P d ~T A (12.16) which indicates that the junction seems to float at some constant differential above the ambient. For constant power loss, a 5°C rise in ambient will cause a 5"C rise injunction temperature. In fact, the increase may be greater because as Tj rises, I CBO and h FE will rise, giving a further increase in I c and junction temperature. The heat removal situation is demonstrated by the electrical analog in Fig. 12.7(a), with two resistances in series. The thermal resistance circuit is 0ja = jc + ca (°C/W) (12.17) where 6 JA = total thermal resistance, junction to ambient 6j C — junction to case thermal resistance (supplied by the manufacturer) Oca — case to ambient resistance of mounting The manufacturer supplies a value for 0, c as well as a thermal derating curve, as shown in Fig. 12.7(b) for a transistor with 30- W dissipation at 25°C case temperature. From the slope of the curve above 25°C we can find that 0jc = T J<U rt-T c (12.18) For this transistor we have T, = 200°C, T c = 25°C, and P t = 30 W so that Ojc = 6°C/W. 40 Transi^or 30 °^ 20 5 Ileal Sink nnr Ambient 10 J lope = 0j 50 100 ISO 200 Case Temperature (°C) (a) (b) Fixure 12.7 (a) Analog of the thermal circuit ;(b) derating curve for a transistor, 30 W at 25°C (77°F) or below. Determination of Output Distortion 293 Substitution of Eq. 12.17 in 12.15 gives us Oca d Vjc (12.19) which determines the allowable thermal resistance for the transistor mounting and heat sink. The use of the derating curve can be shown in the following examples. Example 1: What power rating can we assign to the transistor in Fig. 1 2.7(b) when used in a mounting and heat sink having Q CA = 3°C/W and with Ta - 45°C? We have Oja — Ojc I Oca = 6 + 3 = 9°C/W From Eq. 12.15, - Tj-Ta 200 - 45 155 = 17.2W and this establishes a value for the limit hyperbola for this transistor under the specified temperature conditions. The case temperature at 17.2 W can be found from the derating curve as 100°C. Further data indicate that this transistor (RCA 40316) has a thermal resistance when operating in free air of 30°C/W and a maximum dissipation in that condition of 6 W. Thus the value of JA = 9°C/W for the mounting system provides a considerable improvement in power rating over the free-air condition. Example 2: Consider the transistor (in the previous example) operating at an ambient temperature of 35°C with P d «■ 20 W. What is the maximum allowable value for Oca" 1 - By Eq. 12.19, Oca - 20 ° 2 q 35 - 8.3°C/W From the curve the case temperature will be 82°C. 12.6 Determination of Output Distortion Distortion of the output waveform occurs by reason of the nonlinear nature of the characteristics of the transistors employed. A current transfer curve is plotted in Fig. 12.8, resulting from points chosen along the load line for the amplifier in Fig. 12.5. For large-signal excursions we would anticipate 294 Power Amplilicis H cos oil Figure 12.8 Current transfer curve for the load line of Fig. 12.5. some distortion of the i c waveform, or flattening of positive and negative peaks with the Q point shown. The distorted waveform can be described by a fundamental frequency sinusoidal wave added to various amplitudes of harmonically related sine waves. The harmonics are at integer multiples of the fundamental frequency. The wave may be studied by use of a wave analyzer, which provides an amplitude reading for each harmonic frequency present. We can also analyze amplifier outputs by reading amplitudes from the transfer curve, however, using i c values resulting from an assumed sinusoidal base current signal, as shown in Fig. 12.8. We write the collector current wave as a Fourier series of cosines: ic - A„ (12.20) I A x cos cot -'- A z cos 2cot + ■•■ The amplitudes of the several frequencies present can be determined by evaluation of the A ,A u A z ,... coefficients. The transfer curve can be used to find i c at three points in time, spaced over the positive and negative halves of the input base current cosine wave. Substitution of these values into Eq. Determination of Output Distortion 12.20 results in three equations: At cot - 0, i c «= /„,,, imMx = A a + A,cos (0) H A z cos 2(0) 'mix = A.+ A, - A, since cos (0) = I. At cot = n/2, i c - I c : I c - A. + A, cos (y) I- A z cos 2( T ) I C =A - A, since cos (a/2) = 0, cos n = — I. At cot — 7t, i c = i min : 'mm *■ A„ + A, cos (n) + A, cos 2(n) 'mm — A a — A x -r A % since cos % «= — 1, cos 2w = I. Summarizing, we have 'mix = A„ + A i + A i I c = A a - A 2 'mm = A„ — A, -)" A 2 and solving simultaneously 295 A % - A, = a 'mln - 2/ c A 'mix " 'mln A * 2 The second-harmonic distortion present is the ratio % D z = 4 1 X 100 (12.21) (12.22) (12.23) (12.24) (12.25) (12.26) Since A, is the peak value of the fundamental frequency, the fundamental output power is *»-(4fc)'*»-TM« (,2 - 27) Had we used five points along the input current wave, adding two currents as i x and /, at half amplitude at cot = n/3 and cot = 2b/3, we could calculate additional harmonics. The equations are A. = $(/.„ : '„,,„) + H'« + /,) - Ic 02.28) ^ - -J(' m „ - /.,.) + & - Q ( 12 - 29 ) A - *('m.x + /«,.) - i/ c (12-30) A S ~ |CU - '-!.) - & - y (12-31) ^ = ^(/m., + /„,.) - K<", + y + i'c (12-32) 296 With Z) 2 = ^i x 100%, z> 3 = 4*x 100%, Power Amplifiers 04 = 4** 100%, the total-harmonic distortion is D = JVi+D< s + Di+ ... (12.33) It is convenient to be able to recognize harmonic content from the wave- form and so we present Fig. 12.9. The waveform in Fig. 12.9(a) in which the positive and negative waves are not similar contains predominantly even- order harmonics, whereas that in Fig. 12.9(b) with the two halves as mirror images contains odd-order harmonics. Levels of allowable distortion are subject to individual judgment but a total distortion of 5 per cent is usually tolerated. The allowable level is reduced to less than 1 percent when high-fidelity equipment is involved. In most power amplifiers this low level of distortion can only be achieved through use of negative feedback. < a > (b) Figure 12.9 (a) Even harmonics present ; (b) odd harmonics present. Example: The values for waveform analysis can be read from Fig. 12.8 as 'm.x=l-70 I. = 1.40 / aln = 0.05 i y - 0.55 I c = 0.94 We have 'mix 'rnln - 1.65 'ma* ~f* 'mln = 1.75 h - i, = 0.85 I* + i, = 1.95 Using Eq. 12.28 to 12 .32 we have A. = ^ + i^ - 0.94 = 0.002 The Push-Pull Circuit and Class B Operation 1.65 . 0.85 3 1.75 4 1.65 0.85 297 A, = *f- + ^ = 0.833 A, = ^- 0.47 = -0.033 A,= -0.0083 -0.034 3_ ~6 5 . _ 1.75 1.95 . 0.94 The distortion is predominantly even order, due to the second and fourth harmonics. We find ^3 = 5^x100=1% D« = 0.833 0.034 x 100-4.1% Total distortion : 0.833 D = V4M- P + 4.1 2 = 5.7% 12.7 The Push-Pull Circuit and Class B Operation If we move the Q point down the transfer curve toward the origin, our for- ward swing can still drive the transistor up to i' miX . Therefore we have a greater positive i c current swing and greater power output. The other half of the input wave drives the transistor toward cutoff, however, and we have an unsymmetrical positive and negative wave, as in Fig. 12. 10. While achieving greater power output from a given transistor, we have generated greater even- harmonic distortion. The bias conditions as shown in Fig. 12.10 place the transistors at cutoff for part of a half cycle, the operating condition is intermediate between Class A and Class B, and it is known as Class AB. We can cancel most of the distortion if we add a second transistor Q lt oppositely connected as in Fig. 12.11(a), and achieve the power output of two transistors. The input transformer 7", supplies opposite polarity signal voltages to the two bases, with respect to the midpoint of the winding. On the first half cycle, transistor Q K is driven in the forward direction by the input signal and transistor Q 2 is driven toward cutoff by the opposite polarity input voltage from the other half of the winding. On the next half cycle, the input voltages reverse and Q, is driven toward cutoffand Q 2 gives a full forward output. These output currents combine in the output transformer 7" 2 ; as the transistors appear to operate oppositely on each half cycle, the circuit is called a push-pull amplifier. 298 Figure 12.10 Class AB operation. The circuit action is similar to that of a differential input-differential out- put amplifier; had in-phase signals been applied to the two inputs, the net output signal would be zero. The opposite-phase input signals provide an output after being subtracted in the output transformer, however; that is, +^ — (— A) = 2A. The even-harmonic components are generated in phase and cancel in the output. Figure 12.12 illustrates how the fundamental waves add and the second harmonics cancel upon subtraction in the transformer. Accuracy of harmonic cancellation is assured only with balanced transistor parameters and equal input voltages of 180° phase relation. If we move the Q point to cutoff on the transfer curve, we have com- plete cutoff of one-half of the input wave and can show the action of the second transistor by an opposite transfer curve drawn to the common origin, as in Fig. 12.13. With cutoff bias, the operating condition is Class B. Each transistor supplies an independent half wave and these are combined in the output. Use of the push-pull connection cancels the inherent even-order dis- tortion of the Class B operation and allows us to utilize the higher efficiency and power output of Class B. The current components i Ct and / c , in the output transformer are fc. = h sin cot + J c , ic, = —I a sin cot + I Ci (12.34) (12.35) where /„ sin cot and -/. sin cot are the oppositely phased ac signals and I c , and I c , are the steady 0-point currents. Passing in the windings of transfor- ?>'cc <y V <3 <4 C 9 < :*■ € o O 5 i K i c » \ AAA* , o > o I VVVV " .1 G a c o » c ■ c » °f » .•"""""J c » rk*F V c » — (a )ft o \ k <: \b> / o T, (u) #4* *, i <c, (b) Figure 12.11 The push-pull amplifier. Fundamental » - Second \ / v^ Harmonic |i / > rt-T •— r «2i> Fundamental Second Harmonic fii'urc 12.12 Waveforms in the push-pull output. 299 300 Power Amplifiers Output Q. Figure 12.13 The action of two transistors under Class B conditions. mer 7" 2 in opposite dircclions, these currents are subtractive in their effect on the secondary load so that if I Cl = (— )/ Cl , then ii = K('c, ~ W = 2KI„ sin cot (12.36) The signal currents appear added in the secondary and any dc components are canceled. Thus the steady magnetomotive force that might saturate the iron core is removed and the transformer core is more effectively used. Since the g-point current is essentially zero in a Class B amplifier, the power supply is called upon for sudden current surges as the signal input varies. Power supplies for Class B circuits should maintain constant voltage through these surges or have good voltage regulation. The use of shunt-C filters is advisable for such applications. Since the dc input power is low for zero and small signals, Class B amplifiers arc also preferred for battery-operated equipment. 12.8 Performance of a Class B Push- Pull Amplifier For study of a Class B push-pull amplifier we have the output characteristics for Q, as drawn in the upper half of Fig. 12.14, and with Q 2 in a subtractive relation to Q t in that its characteristics are drawn upside down. The factor common to both transistors is V cc , and the v CE axes are aligned at that Performance of a Class B Push-Pull Amplifier 301 voltage. Since the transistors operate with zero / c at cutoff, the V cc point at which the curves are aligned is also the Q point of the amplifier. Signal swings occur up and down the load line from that quiescent point. The ac load line shown represents the largest output swing, from the upper knee of Q, to the same knee position for Q z . The slope of the load line represents the primary transformer load R,, presented to each transistor, as *, = ££ (12.37) We have assumed the saturation voltage to be small, with a current /„. On the first half cycle, the input signal voltage is forward to Q t and drives the operating point up the load line toward /„; this represents operation below cutoff for Q 2 . On the next half cycle the input voltage is forward to Q 2 and its operating point is driven along the load line toward its /„ value; this is below cutoff for Q x . Figure 12.14 The Class B composite load line. The output current consists of two separate half sine waves, combined into a full sine wave by the output transformer, and gives the output waveform shown in Fig. 12.12. Using what we have learned about such waveforms in the study of diode rectifiers, the dc value of current for one transistor is /dc. - - where I m is the peak of the sine wave. For both transistors /ac - 21*, = ^ (12.38) n 302 and the dc power input to the amplifier is p 2/ M V cc Power Amplifiers (12.39) / =4t, The ac current represented by the composite output wave of Fig. 12.12 is (12.40) and the ac power output to the transformer is P., -- I -fR 1 (12.41) The power conversion efficiency of a Class B amplifier is eff =fe x,00O /« = 2TO x,00% Because of Eq. 12.37, we can write eff . = WUAWccll.) x ,00% = «& X 100% (12.42) 'm'CC 4'o It should be possible to drive the peak of the signal output wave to where I m = h on the transistor curves. Under the maximum signal producing this large peak current we have max eff. = -J. x 100 = 78.5% as the maximum theoretical conversion efficiency. This is a considerable improvement over Class A conditions and is one of the reasons for the wide- spread use of Class B amplifiers. By use of Eq. 1 2.38 we can write the signal power output as P - n 2 HR, (12.43) which shows that the dc power input increases with increasing input signal. The peak transistor dissipation does not occur at maximum output but instead occurs at a signal level that is 40 per cent of that maximum. The peak power loss for use in transistor selection is max/> d = Ai^c=o.20^ 71 f<| A, at which point the conversion efficiency is 50 per cent. (12.44) 12.9 Output Circuits without Transformers The output load of most power amplifiers is a loudspeaker and these usually have a resistance of 3 to 16 £1 At this low level of resistance there is no need for impedance matching and loudspeakers can be directly employed as loads Output Circuits without Transformers 303 for power transistors. Thus the output transformer, with its problems of weight, size, cost, and frequency distortion, can be eliminated in appropriate push-pull circuits which cancel the dc currents which might otherwise appear in the speaker circuits. The usual circuits are derived from the bridge circuit shown in Fig. 1 2. 1 5(a), in which two push-pull circuits drive a common load 7?, between y and z. These circuits are, respectively, Q, and Q 3 as the upper amplifier and Q 1 and Q t as the lower amplifier. The four input windings have a common primary, not shown, and the dots indicate the simultaneously positive ter- minals. Transistors Q l and Q, are simultaneously driven upward in current and Q 2 and Q } are driven downward at the same time. Thus point;' is raised in potential and z is lowered; on the next half cycle y goes down and z goes up in potential so that we have an ac voltage across the load. Points y and z (b) to Figure 12.15 Development of circuits without the output transformer. 304 Power Amplifiers appear to teeter-totter in voltage around point x as a fulcrum. With no signal, points y and z are in dc balance and no dc current passes through the load. The circuit in Fig. 12. 1 5(b) is formed by splitting the first circuit along the common or ground line at g, g; transistors Q, and & are eliminated. Point y moves up and down as Q, and Q, are driven forward and reversed and an ac signal is present. Point x is maintained at its previous dc potential by splitting the power supply into two sections. The value for R L is one-half of load resistance /?,. The circuit in Fig. 12.15(c) evolved to avoid the expense of two power supplies. Since point .v was at zero signal potential to ground in Fig. 12. 1 5(b), it can be connected to actual ground if the large blocking capacitance C is used to avoid short-circuiting the dc supply. Capacitance C is usually of several thousand microfarads so that its reactance will be small compared to the resistance R L of 3 to 16 SI. This R L C combination establishes a low- frequency limit for the amplifier as f - l Jx ~2nR L C 12. 10 Phase Inverters for Push- Pull Input Two equal voltages at 180° in phase are needed for push-pull amplifier input. The size and cost of input transformers can be avoided by use of circuits known as phase inverters; examples are shown in Fig. 12.16. The circuit in Fig. 12.16(a) is called a phase splitter; it consists of an in- (a) (b) Figure 12.16 Phase inverter circuiis. .' Complementary Symmetry Circuits 305 phase output across R E at V n and a reversed-phasc output across R at V 0l . In reality the circuit is an emitter follower with a collector load added. Choos- ing R and R E to provide a gain of unity to V 0l , we have balanced voltages since the emitter follower gain is also near unity. A second phase inverter is that in Fig. 12.16(b), which consists of the preceding circuit with Q 2 added. Both outputs are now taken from low- output resistance emitter followers and this is better for providing balanced and good waveform signals for Class B amplifiers, where there may be demands for large currents to drive the power transistors. A differential amplifier may also be used as a phase inverter to drive a push-pull output stage. 12.11 Complementary Symmetry Circuits The requirement for equal and oppositely phased input voltages for push- pull amplifiers is eliminated by use of a matched pair, npn and pnp, com- plementary transistors. As shown in Fig. 12.18(a), a signal of positive polarity to ground will simultaneously drive the npn unit Q l into forward conduction and the pnp unit Q 2 into cutoff. Thus a common input voltage will give Class B operation of the push-pull circuit. Figure 12.1 8(a) also employs a Darlington compound connection for higher input resistance. The Darlington transistors are also of complementary form. The push-pull circuit is basically that shown in Fig. 12.15(b), with R, as the load. Figure 12.18(b) shows a driver stage using Q t and Q 2 as complementary symmetry transistors with a common input voltage. Their outputs, as emitter followers, provide low-resistance and high-current sources for normal pnp transistors Q 3 and Q 4 in a Class B push-pull circuit whose basic circuit form is that in Fig. 12.15(c). Crossover distortion, as in Fig. 12.17, can appear in the output currents of such amplifiers because of the lack of symmetry in ihc pnp and npn char- acteristics near cutoff. One unit will not turn off at exactly the same currents and voltages as the other turns on. A similar phenomenon may be encoun- tered in Class B amplifiers using the same transistor types and is corrected by bias adjustment and use of ample negative feedback. v w Figure 12.17 Crossover distortion in a waveform. (b) Figure 12.18 (a) Complementary symmetry power amplifier; (b)complementary symmetry driver for a Class B push-pull amplifier. 306 The Class B Linear Radio-Frequency Amplifier 307 12. 12 The Class B Linear Radio-Frequency Amplifier A Class B amplifier, with its accompanying high-power efficiency, may be operated single-ended or push-pull when used at radio frequencies with a resonant load. Because of the near linearity of the transfer curve between input ;' B and output i c , the output voltage is proportional to the driving voltage. The title of Class B linear amplifier is intended to emphasize this point as the amplifier is used to develop radio-frequency power when driven by varying amplitude or modulated radio-frequency voltages. Since the resonant frequency of the tuned load circuit is high at f , in Fig. 1 2. 19, the distortion components generated will have even higher fre- quencies at 2f„, 3f a Having frequencies of two or more times the tuned frequency of the circuit, the harmonics can be well filtered out by a resonant load circuit. To discriminate against these harmonics the load circuit Q is usually maintained in the range from 10 to 15. To retain its property of linearity, the transistor should not be overdriven Resonant lo/„ (■> (b) Figure 12.19 (a) A Class B linear radio-frequency amplifier with tuned load; (b) the n-matching network. 308 Power Amplifiers since that will take it into the flattened saturation portion of the transfer curve above /„„ in Fig. 12.8. A common modification of the resonant circuit, the n-mat citing network in Fig. 12.19(b), provides increased filtering action for the undesirable har- monics. The output power is normally supplied to an "antenna of 50 to 75 Q as R 2 and the load facing the transistor is R, of several hundred ohms. With Q greater than 10, the circuit elements of then network should be S! X c -Si R,R, Q 1 - RJR t Y — $.1.(^1 ^*\ (12.45) (12.46) Since the reactances of the shunt capacitances decrease with higher fre- quencies, they provide low impedance paths which short-circuit the higher- order harmonics to ground. This is why the n circuit is preferred to the T circuit. 12.13 Summary The power output from transistors and tubes is limited by the internal losses that must be removed as heat. Only cooling by conduction or convection is possible at the low operating temperatures of transistors, although heat may be removed by radiation at the temperatures encountered with large-power vacuum tubes. The internal collector loss of the transistor must be removed through the transistor mounting and this is a point needing careful thermal design. Heat sinks are available to improve the heat transfer at temperatures only 100°C(212°F) to 200°C (400°F) above the ambient air temperature. Large-signal excursions for the transistor create nonlinear distortion and harmonic frequencies in the output waveform. Suitable loads are chosen for maximum output conditions on the transistor output characteristics and the resulting harmonic distortion can be calculated directly from the transfer curve, relating i B and i c for a given load. Class A operation has relatively poor power efficiency and low power output from a given transistor or tube but it has small waveform distortion. Class B conditions lead to higher efficiency and greater power output but the even-order distortion is very large. Push-pull circuits can reduce the even- order distortion and negative feedback can be added to reduce the remaining odd-order harmonics. These several circuit modifications reduce the dis- tortion of the Class B condition to allowable levels and the Class B amplifier is especially valuable in the generation of large-power outputs from small transistors or tubes or when the dc power supply is limited in capability, as in battery-operated equipment. r Review Questions 309 REVIEW QUESTIONS 12.1 What is meant by / C eo? 12.2 Why must wc limit the junction temperature of a transistor? 12.3 Define Class A operation; where would you establish the Q point? 12.4 Define Class B operation; where would you establish the Q point? 12.5 Define Class C operation; at what value would you establish the base bias? 12.6 Compare the relative amounts of power output and distortion from a given transistor in Class A, Class B, and Class C operation. 12.7 What is the theoretical maximum conversion efficiency for Class A, Class B, and Class C amplifiers? 12.8 How close to the theoretical conversion efficiency can you expect to operate a transistor Class A amplifier? A vacuum-tube Class A amplifier? 12.9 What is meant by the variable a as related to a transformer? 12.10 A certain transformer is listed as "400 to 3.2 SI." What is meant by this, and what turns ratio would you find? 12.11 What is an ideal transformer? 12.12 What is meant by the locus of collector loss? 12.13 How does l CB0 vary with temperature? 12.14 With fixed base-bias current, what happens to the Q point on a load line when h FE increases? 12.15 Define thermal resistance. 12.16 How do wc use a transistor loss derating curve? 12.17 How can we find the thermal resistance of the transistor case from the derat- ing curve? 12.18 How would Osa change if we add an air blower on the heat sink? 12.19 Why are fins put on a heat sink? 12.20 Define heat sink. 12.21 What is second breakdown of a transistor? Is it damaging? 12.22 What limits the value of anode voltage applied to a triode? 12.23 What is punch-through in a transistor? 12.24 Explain the purpose of an output transformer in a Class A amplifier. How would you determine the turns ratio? 12.25 Define total-harmonic distortion percentage. 12.26 Define second-harmonic distortion. 12.27 What is the difference in form of a wave having even-order harmonics and a wave having odd-order harmonics? 12.28 How many current points would be needed on a transfer curve to find the value of the sixth harmonic? 12.29 What are the advantages of Class B push-pull operation over Class A push- pull operation? 310 Power Amplifiers 12.30 What is the advantage of Class AB operation over Class A operation? 12.31 What feature of Class B push-pull operation makes it especially valuable for battery-operated equipment? 12.32 What is complementary symmetry in transistor amplifiers? 12.33 What is crossover distortion? 12.34 What is the purpose of a phase inverter? 12.35 Why is the phase inverter in Fig. 12.16(b) superior to that in Fig. 12.16(a)? 12.36 Why does a Class B linear radio-frequency amplifier use a tuned circuit for a load ? 12.37 What kind of signals can a Class B linear radio-frequency amplifier handle? 12.38 At what value of output power does maximum collector dissipation occur: (a) In a Class A amplifier? (b) In a Class B amplifier? PROBLEMS 12.1 What turns ratio is needed for a transformer to couple an 8-fi load to a tran- sistor requiring 450 Q ? 12.2 An amplifier with an output resistance of 425 Q is assembled with a trans- former having a turns ratio a = 2.57. What should the secondary load be? 12.3 A transformer is found mounted on an 8-J2 loudspeaker. The turns ratio is measured as 10.5: I. What ac primary resistance will be present? 12.4 A given transistor type has a dissipation rating of 20 W in a certain heat sink. What is the greatest possible power output when one of these transistors is used in Class A service? In Class B service? 12.5 A transformer provides a load of 25 £1 to a transistor with the output curves .' Problems 311 shown in Fig. 12.20(a). The primary has a dc resistance of 5 CI. Find the true Q point, power output, and efficiency for V C c m 30 V, collector loss of 25 W, and driving signal of ± 15 mA peak at the base. 12.6 Determine the second-harmonic distortion for the amplifier of Problem 12.5. 12.7 Draw the transfer i B , i c curve for the load line of Problem 12.5. 12.8 A transistor is derated according to the curve in Fig. 12.21. What is the thermal resistance 6 JC ? 12.9 The heal sink and mounting for the transistor shown in Fig. 12.21 establishes the case temperature at 75°C. What is the power loss in the transistor? 12.10 A silicon transistor is derated according to the curve in Fig. 12.21. For a case temperature of 60°C, what is the allowable power dissipation? 30 20 \ \ \ \ ' \ 10 50 100 150 200 Case Temperature (°C) Figure 12.21 12.11 If the ambient air temperature is 35°C, what is the allowable value of Q c .t for the transistor of Problem 12.10? 12.12 The junction temperature of a transistor is 130°C. The dissipation at a case temperature of 2S°C is 5 W; at a 25°C ambient air temperature it is 2 W. What is the value of 0c? 12.13 A silicon transistor is rated at a thermal resistance d )C - 0.9°C/W with T J[mix) = 160°C. (a) Find the allowable power dissipation if the case is maintained at 50°C. (b) Find the power that could be dissipated if C a = 2°C/W and the ambient air temperature is 35°C. 12.14 A silicon transistor has T Hmtx) = 180°C and 9 JC - 0.7°C/W. If mounted so that Oca = 0.9°C/W, find the power dissipation allowable if the ambient temperature is 30°C. 12.15 A transformer-coupled Class A amplifier drives an 8-fil loudspeaker through a transformer having a — 4.3 : 1 . With a power supply of K t .-c = 36 V, the amplifier delivers 3 W to the loudspeaker. (a) Find the ac voltage across the transformer primary. (b) Find the rms value of loudspeaker voltage. (c) Find the rms value of the loudspeaker current. 312 12.16 12.17 12.18 12.19 12.20 12.21 12.22 Power Amplifiers For the following current measurements from a waveform, find the second- harmonic distortion percentage: / m „ = 0.9 A, ; mln - 0.47 A, and I c = 0.65 A. The load resistance through which this current passes is 95 CI. What is the fundamental power output? If the (2-point dc current is 0.22 A in Problem 12.15, find the conversion efficiency. Find the collector dissipation for a Class A operated transistor with V^ = 30 V, I c = 2.0 A, and ac current of 0.7 A. The load is supplied by a trans- former with a = 2.2: 1 ; the secondary load is 10 fi. What is the signal power output? An amplifier has only second-harmonic distortion. (>) If »m.x = 250 mA, i m , n = 5 mA, and I c = 100 mA, find the value of the second-harmonic distortion D t . (b) If a transformer of a = 4 : I couples a 10-fl load to this amplifier, what is the fundamental frequency power output? Using the transistor in Fig. 12.20(b) with V cc = 40 V, I B = 60 mA at the Q point, with 20 Q given by the transformer load, find (a) The fundamental power output with an ac sinusoidal input of ±40 mA peak. (b) The second- and third-harmonic percentages. (c) The conversion efficiency. A Class B push-pull amplifier is supplied by V cc = 50 V and the signal swings the collector voltage to ».- mln = 10 V. The dc loss in both transistors is 40 W. (a) Find the power being delivered to the load. (b) Find the conversion efficiency. With a transformer load of 30 SI = /?, for each transistor, a Class B push- pull amplifier takes 0.75 A from the dc supply with a particular input signal. (a) What is the ac power output? (b) If the dc supply is at 40 V, what is the transistor power loss and the con- version efficiency ? .' 13 Oscillator Principles Oscillator circuits are the generators of our radio frequencies. A primary requirement is that the frequency be stable but, under conditions of varying supply voltages and varying temperature, sufficient stability is difficult to achieve. There is a variety of circuits available but fundamentally those to be studied here all depend on positive feedback for their operation. 13.1 Oscillator Feedback Principles In the circuit in Fig. 13. 1 the voltage fed back from the amplifier output supplies the total input and since V„ — —AV„ then V,= -APY, (13.1) from which (1 + Afi)V, - If an output is present however, then V, ■£■ and therefore 1 + Afi = Ap=-l (13.2) 313 314 Oscillator Principles Figure 13.1 The basic feedback oscillator. which was the condition wc found in Chapter 9 that would lead to oscillation in a feedback amplifier. Here we want the circuit to oscillate and so the expression above states two requirements for oscillation to occur: / 1. That/iy? = -1. 2. That the net phase shift around the feedback loop be 0° or 360° or 2/i x 180°, where n is 0, 1,2,3, In Fig. 13.1 the amplifier provides its own input and initially the gain must be such that \Af}\> 1. An initial turn-on surge or noise voltage provides V, at the input and this is amplified to the output. This amplified output is fed back to the input as a larger signal. The process is repeated at successively greater amplitudes until the output becomes limited at cutoff and saturation. By operation to those limits the gain is reduced to an average level called for by Eq. 13.2 and a steady level is maintained. The frequency of oscillation adjusts itself so that the phase shift require- ment is satisfied. Limitation of amplitude by cutoff and saturation implies distortion. The resultant harmonic frequencies can best be filtered out by use of a resonant circuit for the /? network. High Q (high C) there provides better discrimina- tion against the harmonic frequencies and also causes the circuit to oscillate more precisely at the resonant frequency of the tuned circuit. The reactance network in Fig. 13.2(a) provides feedback and 180° of phase shift between the output and the input; the FET provides 180° of additional phase shift to meet the phase requirement of 360° for oscillation. Reactances X,, X lt and X } must be resonant and the frequency of oscilla- tion adjusts to make this occur. We know that the resonant frequency will make X, + X 1 + X, = (13.3) For this equation to be true, one or two but not all three of the reactances must be negative and capacitive. This shows us the possibility of two basic Oscillator Feedback Principles 315 r4T— s - X, — J — x 2 — * • ' c o fc-t x, (a) (b) Figure 13.2 (a) Tuned-circuit feedback; (b) the equivalenl circuit. i Figure 13.3 (a) Colpitts oscillator without bias circuits; (b) Hartley oscillator circuit. circuits as in Fig. 13.3, the Hartley oscillator with two inductances (a tapped coil) and the Colpitts oscillator with two capacitances. For the FET circuit in Fig. 13.2(b) wc have A = -g m R where R is the resonant resistance of X l in parallel with X, + -*V The circuit as drawn also shows us that P X> + X, from our previous work on feedback amplifiers. From these equations it is possible to show that the gain requirement for oscillation leads to £-> AT, (13.4) which can be satisfied. The frequency requirement of Eq. 13.3 satisfies the phase requirement and the circuit will oscillate. 316 Oscillator Principles In order that g m be positive, Eq. 13.4 shows that X x and X 2 must be the same type of reactance; X 3 must therefore be of the opposite type to satisfy Eq. 13.3. 13.2 The Hartley and Colpitts Oscillators The Hartley and Colpitts circuits in Fig. 13.3 are the basic feedback oscillator circuits. Analysis of the Colpitis oscillator provides an equation for the frequency of oscillation: ft = , ~ J —== (13.5) 2njl C t C 1 C f "at c, + c 2 The first term under the radical is the resonant frequency of the L and equivalent C values of the tuned circuit. The second term under the radical shows that variation of the transistor parameters can have an effect on the frequency of oscillation. The effect is small because h a . < h,,. For design, we use (13.6) /o = 2*V Z C,Q In^LC C, +C 2 We are normally concerned with oscillator frequencies of I MHz or over and a variation of 0.01 per cent at 1 MHz represents a shift of only 100 Hz; later we shall discuss oscillators in which such a shift is not negligible. The gain requirement for oscillation for the Colpitts circuit gives hf.^. £r + hJ'o,-^ (13.7) and, with C 2 = C,, we have no difficulty in meeting this requirement. The Hartley oscillator can be similarly analyzed for frequency of oscilla- tion. Again a small additive term is dependent on hjlt u and the frequency can be slightly affected by transistor parameters. Basically the frequency of oscillation is where L is the total inductance of the tapped coil. The necessary gain requirement makes h,, a function of LJL, ; again we have no problem in meeting this requirement since we may make L, = L t . 13.3 Practical Transistor Oscillators The basic circuits in Fig. 13.3 do not include the bias circuits and associated blocking and bypass capacitors that are required for normal operation. These oscillator circuits are shown complete in Fig. 1 3.4. ' Practical Transistor Oscillators 317 (a) (b) Figure 13.4 (a) Practical Colpitts oscillator circuit ;(b) Hartley oscillator circuit. Resistors /?,, R 2 , and R E provide the bias with initial design values setting the Q point a little more toward cutoff than for normal Class A operation. Full Class B or Class C biasing cannot be used because we would ihcn have zero initial current. This would mean that there would be no way for the oscillations to start. Our design values for these bias resistors are determined by the methods of Chapter 5. Capacitor C E is selected to have a reactance less than R E /\0 at the operating frequency. The two blocking capacitors C c are placed to isolate the bias voltages to the transistor and should have reactances of only a few hundred ohms. The radio-frequency choke, RFC, passes the dc collector current but by reason of its inductive reactance it prevents current at oscillator frequency from reaching the power supply, lt should have an inductive reactance that is much larger than the reactance of a blocking capacitor, or lOA'c- (13.9) The frequency of oscillation in each circuit will be very close to the reso- nant frequency of the tuned circuit when stray capacitances of the wiring are included. The tuned circuit is sometimes called a tank circuit because it serves as a reservoir of radio-frequency energy, part of which is inductively coupled to the output as V„. While values of g m and h fc have been indicated as minimums to assure that oscillations will start, the value of C 2 is usually equal to C, in the Colpitts circuit because equal capacitance split-stator tuning capacitors are generally 318 Oscillator Principles available. In the Hartley circuit the choice of the tap position on L is arbitrary. It is usually located so that L z is two to four times greater than L, ; this does not overdrive the transistor and results in a lower harmonic content in the waveform. The Armstrong oscillator circuit is shown in Fig. 13.5(a). If examined carefully, it can be seen that it is basically a Hartley oscillator circuit (tapped inductor) with only the base circuit tuned. The power supply is introduced in series with the collector inductance, and the radio-frequency choke prevents high-frequency currents from entering the power supply. Instead, these currents are provided with an easy path to the emitter and ground through the bypass capacitor C c . (b) Figure 13.5 (a) Armstrong variation of the Hartley oscillator ; (b) tuncd-collcctor oscillalor, lapped-collcctor coil. Crystal Control of Frequency 319 The circuit in Fig. 13.5(b), is a tuned-collector oscillator, also basically a Hartley circuit. In order to raise the Q of the tuned circuit, the collector is connected to a lap on the circuit inductance. 13.4 Crystal Control of Frequency Piezoelectric quartz crystals arc of hexagonal form, with atomic plus and minus charges arranged in the unit crystal as in Fig. 13.6(a). Being symmet- rical, the charges balance and the crystal is electrically neutral. Horizontal pressure from the left and right reduces angle tf> and the negative charge (1) moves up and the positive charge (2) moves down. This movement destroys the symmetry and the crystal shows a negative charge at the top surface and a positive charge on the bottom surface. Horizontal tension enlarges angle <j> and the charges move in the opposite directions. Therefore the charge LA c,± *c •>->c k (a) (b) x ("ul (0 Id) Figure 13.6 (a) Piezoelectric charge orientation; (b) crystal equivalent circuit; (c) crystal in the holder; (d) axes of the basic crystal cuts. 320 Oscillator Principles appearing on the upper and lower crystal surfaces alternately changes with variation of horizontal pressure. Conversely, if electrical charges are placed on the upper and lower surfaces by applying a voltage, a mechanical deforma- tion of the crystal occurs in the horizontal direction. An alternating voltage applied to the top and bottom crystal surfaces will cause the crystal to vibrate. If the time of travel of the mechanical vibration through the crystal is equal to a half cycle of the alternating voltage, then mechanical resonance occurs. The amplitude of the vibrations and the electrical voltage can be large. Rochelle salt is a very active piezoelectric material. It is easily damaged by moisture, however, and its use is confined to microphones. Quartz gives smaller output voltages but is mechanically very stable. The oscillation is electromechanical in nature and the frequency of resonance is dependent on a thickness dimension of the crystal. Electrical circuits employing piezoelectric crystals can be analyzed by replacing the crystal with its equivalent electrical network, Fig. 13.6(b). The magnitudes of L„ C„ and R, of the network depend on the way the crystal slice is cut and its thickness, as in Fig. 13.6(c). Capacitance C h is that of the mounting electrodes, usually electroplated onto the faces of the thin quartz slab. The valuable property of the quartz crystal is its sharp resonant response, which gives it a high equivalent Q. The Q is typically 30,000 but can reach 500,000 in units mounted in evacuated cans to eliminate air damping of the vibrations. With a Q of 30,000, a crystal resonant at 4 MHz will have a bandwidth of only 133 Hz. The .v and y axes of the crystal are shown in Fig. 13.6(c), with x- and >'-cut crystals sliced perpendicular to the designated axes. These crystals have frequencies that vary with temperature but by an appropriate orientation of the angle of cut a zero temperature coefficient of frequency can be obtained. Resonant frequencies from about 10 kHz to above 20 MHz are possible with usable crystal thicknesses and higher frequencies can be generated as har- monic frequencies. Several crystal oscillator circuits are shown in Fig. 13.7. That in Fig. 13.7(a) uses the crystal as a feedback clement, with maximum positive feed- back and oscillation at the crystal series or low-resistance resonance. The tuned circuit is adjusted near the crystal frequency and serves as an output waveform filter, the exact oscillation frequency being set by the crystal. Series resonance occurs when the left branch of the equivalent circuit appears resistive, at *-=&* <,3 ■ ,0, The resistance of this branch of the circuit at resonance is R, since the reac- .' Crystal Control ol Frequency Cc 321 Crystal V — WW tt ii Hf-o -/ -i Cr (a) Figure 13.7 (a) Transistor crystal oscillator, collector tuned; (b) FET-tuncd output oscillator. tances of L, and C. arc equal, opposite in sign, and cancel. This is the fre- quency of maximum positive feedback. The crystal electrodes form the capacitance C h with quartz as a dielectric. Capacitance C A causes a parallel resonance, with a resonant frequency f p determined when the reactances of the two branches are equal, as Xl. ~ Xc, = Xc, 1 I 2nf,L, - But this can also be written as 2nf p C, (13.11) p«-i. 2nf p L e m ^ ■!■ ^ 2xf,\C* Cj f '_ " InjL.C where C is the equivalent series value of C, and C k , C. + C The effective circuit resistance is R - & (13.12) (13.13) (13.14) ajid is very high. The parallel-resonant frequency is very slightly higher than 322 Oscillator Principles The circuit in Fig. 13.7(b) employs the crystal in its parallel-resonant high-resistance mode as a resonant circuit in the gate, in a drain-tuned FET oscillator. Again, the tuned circuit supplies a frequency-selective filter but the crystal parallel resonance fixes the oscillating frequency. Changes in the load on the oscillator will alter the gain and thereby cause a change in the Miller-effect capacitance. This C„ is in parallel with the tuned circuit of an LC oscillator and shifts the frequency. The shift can be reduced by the use of large tank capacitance and small L in those circuits. Greater stability is given by use of a crystal since the Miller capacitance appears in parallel with C h . With an alteration of C h , which is in series with C,, the effective tuning capacitance C is not appreciably altered. In one example, a change of 10 per cent in C h changed the crystal frequency only 0.003 per cent. To isolate an oscillator from such changes in load that might affect the frequency, the oscillator is often followed by a buffer amplifier. This is designed to present a constant and high impedance load to the oscillator. An emitter follower is suitable for this purpose. 13.5 Resistance-Capacitance Feedback Oscillator Variable LC oscillators tune over a frequency range that is proportional to l/VC. Available variable capacitors rarely have a maximum-to-minimum capacitance ratio greater than 10: I so that LC oscillators usually tune over ranges of VTO = 3.1. The function of the LC circuit is to provide the needed phase shift, however, and RC circuits can do this with a frequency range proportional to C, or over a 10: 1 frequency range. This decade frequency range is of advantage in laboratory oscillators, used in a circuit like that in Fig. 13.8. C»5! Figure 13.8 Basic Hewlett-Packard resistance-capacitance laboratory oscillator. Comments 323 An operational amplifier provides ~A gain internally, with 360° of phase shift ; the /? circuit of the series RC and parallel RC elements need provide no additional shift at the feedback frequency. With P- Z t /_0i +ZzL0i (13.15) z t + z t and the zero phase shift requirement can be met if 9, — 8 2 . With the zero phase shift occurs with /?, — R 2 — R and C, = C 2 = C at a frequency /o = 1 (13.16) 2nRC The needed gain, with negative feedback provided by R 3 and R t in the configuration of the operational amplifier, is A -k^ (13.17) The negative feedback should provide a gain slightly greater than 3 so that oscillations will start. For instance, we might choose R 3 — 350,000 fl and R t = 1 00,000 fi. With negative feedback present to limit the gain close to the critical value, the oscillator does not operate far into cutoff and satura- tion; as a result, excellent sine waves can be obtained at the output. The R j, R A resistors are often changed to a scries resistor R 2 that supplies current to a low-power lamp as R t . Feedback is taken across the lamp and is small when the lamp is cold at low output. As the output increases, the lamp resistance increases much more rapidly than the current; the gain is reduced and the output regulated to a constant level. The gain is maintained just over the critical value of 3, cutoff and saturation are avoided, and excellent output waveform is obtained. 13.6 Comments The oscillator serves as the source for high-frequency voltages. The feedback circuits discussed here are not the only forms but they are most generally used. The stability of oscillator frequency is the most important criterion of performance. The problem of stability of frequency would be a simple one if the oscillator were operated in isolation, at constant temperature, with unchanging components and constant voltages, and with no power taken from the circuit. Difficulties arise when we supply power from oscillators built with practical components and operating in normal environments. 324 Oscillator Principles At one time a crystal oscillator was almost the only means of obtaining stable operation; advanced materials and isolation of the oscillator function has now led to drift rates of only a few hertz per hour at megacycle fre- quencies, when using the tuned-circuit forms. REVIEW QUESTIONS 13.1 Is the feedback negative or positive in an oscillator? 13.2 What two requirements must be satisfied to make an oscillator from a feed- back amplifier? 13.3 In a feedback amplifier, what is the minimum value of /? needed for oscilla- tion? 13.4 What is the value of Aft for sustained oscillation? 13.5 An amplifier has a gain of 5; how is this gain reduced to the limiting value when the amplifier oscillates? 13.6 Explain the process of buildup of oscillations in an LC oscillator. 13.7 Explain the process of buildup of oscillations in an Armstrong oscillator. 13.8 What circuit determines the frequency of oscillation in a Hartley oscillator? The Colpitts oscillator? The Armstrong oscillator? 13.9 How is feedback provided in an Armstrong oscillator? 13.10 In what way is a crystal-controlled oscillator better than an LC oscillator? 13.11 Why is quartz a suitable material for oscillating crystals? 13.12 What is the effect of variation of output load on the oscillating frequency of an oscillator? 13.13 How does output load affect the frequency of an oscillator? 13.14 What is meant by the temperature coefficient of a quartz crystal? 13.15 What is the phase shift requirement for the /? circuit of an RC oscillator? 13.16 What gain must an amplifier have to be used in an RC oscillator? 13.17 What is the purpose of using a tungsten incandescent bulb in the emitter or ground lead of an RC oscillator? PROBLEMS 13.1 In Fig. 13.4(a), the Colpitts oscillator has C, = C 2 = C and L = 150 fiH. Find C, - C 2 for oscillation at 1.5 MHz. 13.2 In a Colpitts oscillator in Fig. 13.4(a), C, = 250 pF, C 2 = 100 pF, and L - 300 ptH. What is the frequency of oscillation? 13.3 A transistor Colpitts oscillator has L = 37 pH, C, = C 2 = 310 pF, Q = 15, //„ = 5 x 10" 6 mho, and h lt = 800 Q. Find the frequency of oscillation; show the effect in hertz due to the correction term involving h ,lh„. Problems 326 / 13.4 13.5 13.6 13.7 13.8 13.9 In the circuit in Fig. 13.4(b), oscillating at 3.7 MHz, determine if C c = 0.05 ^F, L RfC = 1.5 mH, and C E =0.1 //F are suitable values. A quartz crystal has equivalent L, = 3.66 H, C, = 0.032 pF, C k = 6 pF, and R, = 4500 CI. What is the Q at the series resonant frequency? A quartz crystal has L, = 0.6 H, C. - 0.022 pF, C h = 5.42 pF, and Q = 20,000. Find /„ and f„. The crystal of Problem 13.6 has a trimmer capacitor C m across C h to vary the oscillator frequency. If the trimmer is variable from 2.8 to 9.8 pF, find the possible range of variation of crystal frequency. (Use a calculator). A quartz crystal has L, - 250 H, C, = 0.04 pF, R = 1800Q, and C h = 7 pF. When used to tunc the base circuit of a transistor with C lt — 30 pF, find the frequency of oscillation. The equivalent circuit is that shown in Fig. 13.9(b). In Fig. 13.9(a) the circuit is to oscillate and C - 0.1 /iF, L = 0.15 H, and R, = 20,000 Si. (a) Find the gain A. (b) Is the phase requirement satisfied at resonance? (c) What is the value of /?? (d) What is the output frequency? 50.000 n -WW ::C h irC -°£ (b) Figure 13.9 13.10 Choose the RC elements for an oscillator as in Fig. 13.8, for operation at /„ 2 kHz. Minimum gain is to be 3.2. 13.11 If R, = /? 2 = 10.000 Q, C t =Ci= 0.05 ftF, R 3 = 5000 Q, and R 4 = 1500 £2, what is the frequency of oscillation of the RC oscillator of Fig. 13.8? What is the amplifier gain with feedback? 13.12 In Problem 13.11, if M - 350, choose values for /? 3 and R t to assure that oscillations will just start. 13.13 In Problem 13.12, C, and C 2 are changed to a split-stator or double variable capacitor with a range from 30 to 330 pF (each section). With R, ■ Ri — 10 5 £2, what is the tuning range of the RC oscillator? 14 Modulation and Detection Electromagnetic radio waves propagate well through space only if the fre- quency is high, at least above 200 kHz. Speech and music frequencies lie in the band below 15 kHz; television picture signals utilize a video band ranging from 30 Hz to 4.5 MHz. To radiate such signals through space adequately requires that the base band frequencies be translated to appropriate channels in the radio-frequency spectrum that will carry the signals. These channels presently cover the frequency range from 200 kHz to many gigahertz. Such translation or conversion of frequency is accomplished by the process of modulation. Detection, or demodulation, is the name for the reverse process by which the desired signals are recovered from the radio-frequency carriers and made audible or visible as in television. 14. 1 Fundamentals of Modulation An alternating voltage can be expressed as a function of time as v = A cos {In ft + B) (14.1) where A ns peak amplitude of the wave /= frequency in hertz 6 — phase angle t = time 326 The Frequency Spectrum In AM 327 In telephone and radio transmission we want to convey information to ihe receiver. The wave of Eq. 14.1 can carry information only through its presence or absence. The telegraph is an example of such an on-off signal but the telegraph has been limited in its rate of transmission of information. To send information as fast as it is generated, or in real time, requires that a characteristic of the radio wave be varied at the real time rate. Equation 14.1 has two characteristics capable of being varied with time in accordance with the information we want to transmit. Thus we have two basic methods of modulation of an ac wave, as 1. Amplitude modulation (AM), in which the wave amplitude A is caused to vary in accordance with the amplitude of the modulating signal. 2. Frequency modulation (FM), in which the frequency / of the wave is changed in accordance with the amplitude of the modulating signal. Actually, FM is a subproccss of a more general form known as angle modulation, as is phase modulation (PM) in which 6 is caused to vary with the modulating signal; however, FM is most generally used. Another class of systems does employ the method of the telegraph but turns the signal on and off at a very high rate and generates very short pulses for transmission. The information signal is sampled at a rate of several thousand per second and a characteristic of the pulse is varied to represent the amplitude of each sample. We have several possibilities: 1. PAM, pulse-amplitude modulation, in which the amplitude of the pulse is varied by the sample amplitude. 2. PDM, pulse-duration modulation, in which the duration of the pulse represents the sample amplitude. 3. PCM, pulse-code modulation, in which a coded train of pulses repre- sents the sample amplitude. The PCM system is becoming widely used because of its freedom from noise and distortion in the transmitting path, wire, cable, or space. In the reception of PCM we do not need to receive an accurate pulse waveform. By transmitting the sample amplitude in a code of pulses, we need only to deter- mine that a pulse was sent or not sent. The binary code of Chapter 16 is generally employed in generating the pulse trains, which are decoded back to sample amplitudes at the receiver. 14.2 The Frequency Spectrum in AM The frequency of the radio-frequency wave will be designated f c , as the car- rier frequency on which the informational signal is to be modulated. The informational signal from speech, music, or the dots of a TV picture will be 328 Modulation and Detection assigned a frequency/,. The frequency/, will be only one of a large band of frequencies making up the complete music or TV picture spectrum; we use this one frequency as an example of what happens to every such frequency. The signal frequency/, is smaller than the carrier frequency/ on which it is to be modulated. The signal frequency can be written as v, -- V, cos 2b/,/ (14.2) and the carrier frequency on which we wish to modulate the information signal is v c - A cos 2b// (14.3) from Eq. 14.1, after dropping the constant angle as having no meaning here. In amplitude modulation we vary the coefficient A with the informational signal so that A = V c |- V, cos 2b/,/ = K,(i+£cos2b/,/) <"•<> The modulation factor is «.=£ (14.5) and A = V c (\ -\- m a cos 2jif,t) (14.6) In AM systems it is not desirable for m„ to exceed 1 .0 or 100 per cent because of excessive distortion that is generated. Substitution of Eq. 14.6 for A into Eq. 14.3 gives us an expression for the amplitude-modulated wave: v = V c {\ + m a cos 2b/,/) cos 2b// (14.7) = V c cos 2b// I m„V c cos 2b// cos 2b// (14.8) The first term is the carrier and the second term can be simplified if we use the trigonometric identity cos a cos b = \ cos (a -f- b) + £ cos (a — b) showing that the second term actually consists of two waves. We can then state the amplitude-modulated wave as v = V e cos 2b// + '-f V c cos 2b(/ + /)/ + y" V c cos 2b(/ - /)/ (14.9) The amplitude-modulated wave consists of three frequencies, the original carrier at/ and two side frequencies. The upper side frequency appears as the sum of the carrier and modulation frequencies,/ +/, and the lower side frequency appears as the difference of the carrier and the modulation fre- The Frequency Spectrum in AM 329 quencies,/ - /. If/ is small, then the three frequencies are closely grouped and centered on/. The resultant waveform is shown in Fig. 14. 1 , with the constant amplitude carrier in Fig. 14. 1(a) and the modulated wave in Fig. 14.1(b). The modulated wave is not the result of simple addition of two frequencies but is the sum of three frequencies of Eq. 14.9. Amplitude modulation occurs because of the product of two frequencies as found in Eq. 14.8. Such a product is aneccssary condition for any method of amplitude modulation. If the modulating signal is one of many frequency components in speech or music, as examples, then many side-frequency pairs exist, and the groups of side frequencies are called the upper and lower sidebands. Figure 14.2(a) shows the spectrum of an AM waveform in which a carrier at / has been modulated by a frequency/, generating two side frequencies. In Fig. 14.2(b) we have an AM spectrum in which a carrier at/ is simultaneously modulated by three signals at 1000, 2000, and 4000 Hz. The information-carrying signal has been translated by amplitude modula- ta) Figure 14.1 (a) Unmodulated waveform; (b) ampliiude-modulatcd wave, m fl = 0.5. Carrier Carrier Lower Sideband jj. Upper Sideband J_L_L fc-f, fc fc+f, (a) -4k lk/ c +Ik +4k 2k +2k (b) Figure 14.2 Frequency spectra for AM modulation. 330 Modulation and Detection tion to a different frequency / c , ideally without distortion. The carrier/, can be placed anywhere in the radio spectrum for ease in transmission over wires or through space or for better conditions of amplification. The bandwidth occupied by the signal has been doubled since we now have two sidebands. That is, the modulated wave represented by the spectrum in Fig. 14.2(b) with f t = 1 MHz would have sidebands extending from 0.996 to 1.004 MHz, a total bandwidth of 8 kHz and twice the frequency of the highest-frequency modulating signal. With frequencies scarce in our crowded radio bands, this doubling of bandwidth is one of the deficiencies of the AM system of modu- lation. The waveform of an AM wave would appear on a cathode-ray oscillo- scope as in Fig. 14.1(b). Measurements A and B may be made to find the value of m„ from the pattern; that is m a =» A- B A B (14.10) 14.3 The Power Spectrum in AM Equation 14.9 tells us that the carrier has an amplitude V r and when the modulated wave is applied to a resistive load R, the power due to the three components in double sideband AM (DSB) is Carrier power: (14.11) (14.12) te R Upper sideband: p ml V\ ml p ' 4 R ' ' 4 c Lower sideband: p _ ml V} _ ml p 4 R -- 4 c (14.13) (14.14) The total power in an AM wave is therefore P-P.(\ I f) The total power in the sidebands is ml/2 limes the power in the carrier and is divided among the many frequency components, each frequency having its own value of m. such that m: ml. m- mi At m„ = 1 .0 or 1 00 per cent modulation, the sideband average power with sinusoidal modulation is 50 per cent of the carrier power and the total average The Diode Modulator lor AM 331 power is 150 percent of the unmodulated carrier power. The signal sidebands employ only one-third of the total power of an AM wave at lOO per cent modulation, the other two-thirds being present in the carrier. In Fig. 14.1(b) the peak above V c \%mV c and at m - 1.0, the peak voltage is 2V S and double the carrier level. The equipment must be designed to with- stand such a voltage at peak modulation. With 2V C at the peak on full modulation, the power is 4V-/R = 4P C and power peaks of four times the normal unmodulated carrier must be supplied. A radio station is rated at a carrier power of 1000 W. To reach 100 per cent modulation we must supply 500 W of average modulating power and there will then be 250 W average in each sideband. At 10 per cent modulation i ma -_ 0.10) the carrier power is still 1000 W but by Eq. 14.14 the average sideband power is only 2.5 W. Since only the sidebands are usable power at the receiver, this low modulation percentage gives a very poor power effi- ciency for information transmittal. Accordingly, the modulation factor m„ is normally maintained near 1.0. 14.4 The Diode Modulator for AM Amplitude modulation is often generated by use of the nonlinear voltage- current curve of a diode or that of the transistor emitter-base junction. Let us approximate the diode curve in Fig. 14.3(a) by use of a linear curve added to a parabolic curve, as / = fl ,« -\ dzV 1 (14.15) In Fig. 14.3(b) two voltages arc applied to the diode and load circuit, resonant at frequency f c : v=V c cos 2nf c t -f V, cos 2nf,t (14.16) 1 M 1) ft© Tu /■ — s. C o ,u o o o x ti o '■(: (a) Figure 14.3 (b) (a) A diode characteristic; (b) simplified diode modulator. ■ 332 Modulation and Detection where V, < V c and f, </ c . Substituting this voltage expression into Eq. 14.15, we can develop an equation for the circuit current as (14.17) i = a, V c cos 2nf c t + a, V, cos 2nf,t -|- a,V\ cos 2 2nf c t + a 1 V) cos 2 2nfj - 2a 2 K c K, cos 2jr/ J r cos 2n/ c / By trigonometric identity, we have cos 2 a = \ cos 2a + £ and the third and fourth terms of Eq. 14.17 can be modified to a % V\ cos 2 2nf c t m ^p[cos 2n(2f c )t + 1] a 2 KJ cos 1 2nf,t - ^[cos 27r(2/> + i-] But 2/ and 2/, are double frequencies or second harmonics. Rearranging Eq. 14.17 and using these equations involving the second- harmonic frequencies, we have i - a, V c cos 2nf c t + ^p[oos 2ti(2/ c )/ + JU + a, K, cos 2b/,/ + ^[cos 2n(2f,)t + ^-1 + 2a 2 V e V, cos 2r/,/ cos 2»/ c / (14.18) This current passes through the tuned circuit, resonant and having a high resistance only near frequency /. The frequency 2f c is far removed from/, being a second harmonic, and so are frequencies/, and 2/ as modulating frequencies, and the dc terms a 2 K c 2 /2 and a 2 K;/2. Only the first and last terms of Eq. 14.18, involving frequency/, will produce appreciable voltages across the resonant circuit. Thus that circuit acts as a filter to remove the fre- quencies we do not want in the modulator output. Therefore, the effective output voltage is v = a,/f,K c cos 2nf c t -I 2a 2 R„V,V c cos 2nf,t cos 2nf c t (14.19) where R p is the resonant impedance of the circuit. This expression shows the frequency product term predicted as necessary for amplitude modulation. We can reduce Eq. 14.19 to v = a , R P V C ( 1 -• -^ V, cos 2nf,t) cos 2nf c t (14.20) which shows the voltage in the form of Eq. 14.7 as an amplitude-modulated wave. This process is known as a small-signal or low-power method of modula- tion. High-Power-Level AM Modulation 333 14.5 High-Power-Level AM Modulation A method of amplitude modulation better suited to high-power use is that of power conversion in the Class C modulated amplifier shown in Fig. 14.4. With the input at/, the high-frequency current output is linearly related to the supply voltage to the amplifier. If that supply voltage is varied by a Class B V c cos 2itf c t Modulated Amplifier Class B Modulator Signal o o at/, o ■ Modulated Output «r '4 /c V t cos 2jt/,/ V cc fa) Output Current Figure 14.4 (a) High-level AM modulator circuit ; (b) resultant output current. 334 Modulation and Detection amplifier as modulator, wc have ». = Vcc + V, cos 2nfj = V cc (\ + m.cos2nf,i) (14.21) The current lo the output tuned circuit varies in a similar manner, giving / = -^(1 I m, cos 271/,/) cos 2nf c t (14.22) and this represents an amplitude-modulated wave, with carrier at f c and sidebands/. • /, and f c — f„ Eq. 14.7 and 14.9. With the supply voltage varying at the/, rate, then the carrier frequency current in the lank circuit will have an envelope shape corresponding to the modulating signal. The current from the dc supply is I c since the modulation-frequency variation is up and down from the steady level and averages out. The dc sup- ply furnishes the steady carrier power K cc ./ C and the modulator must furnish the power for the sidebands, at maximum being V cc l c /2. The output trans- former of the Class B amplifier must be adequate for this level of power. The secondary load resistance for the Class B modulator must be known in order lo specify the turns ratio of the transformer. The resistance into which this transformer delivers the sideband power is that of the modulated amplifier at the modulation frequency. This is „ _ modulation component of secondary voltage * modulation component of secondary current ^ m a V cc cos 2nf,t _ V cc m a I c cos 2nf,i I c (14.23) which is simply the dc resistance represented by the modulated amplifier. Another form of amplitude modulation forces a current of one frequency through a resistance or impedance whose magnitude is varied at a second frequency. Thus v = /, cos 2nf,i x R cos 2nf c l (14.24) This shows directly the frequency product term needed for amplitude modula- tion to take place. This method is used in low-frequency servo systems by variation of an inductance at the carrier rate. 14.6 Linear Detection for AM Signals To recover the useful information from an AM wave we normally use a diode detector or envelope demodulator. The circuit in Fig. 14.5(a) acts much as a half-wave diode rectifier with a shunt-capacitor filter. Capacitor C is chosen so that the parameter//?C is in the range of 30 to Linear Detection for AM Signals 33S P -* — r u C'ss R — i AVC (a) fb) FiKure 14.5 (a) Linear diode detector circuit; (b) output waveform. 200, as done for the rectifier. The capacitor charges to the peak of each carrier cycle and holds that voltage until the next positive half cycle. With an ampli- tude-modulated wave as an input signal, v = V&\ + m. cos 2nf,t) cos 2nf c t The voltage of the capacitor at the carrier peaks is V. = V c {\ + m a cos 27i/./) (14.25) as shown in Fig. 14.5(b). Since m„ = V,\V e> we have ^ = r«+^cos27r/,/ (14.26) This shows that in the voltage across the load R wc have recovered the origi- nal modulation signal and also have a dc term equal to the carrier amplitude of the received signal. The voltage K„ appears across R and C c blocks the dc component but passes the modulation frequency /, to the output of the detector. Practical circuit values are shown in Fig. 14.6 for/, * 2 MHz. While R and C are chosen so that/ c /fC is large, they should be chosen so that/,/?C is approximately given by I max/flC < 2nm a (14.27) Such a choice ensures that RC is small enough that at frequency/ the capac- itor C can discharge between cycles of/, and thus its voltage is able to follow Figure 14.6 A practical detector circuit for AM. 336 Modulation and Detection changes in V„ the information signal amplitude. Distortion results if Eq. 14.27 is not approximately satisfied. 14.7 Automatic Volume Control (AVC) In radio reception it is desired that weak signals be amplified more and strong signals be amplified less so that the output level of all signals is about the same and remains so even though signals/orfe and weaken in transmission. The dc term in Eq. 14.26, equal to the received carrier level, provides a Signal Output Circuit — Output (a) V r/ -°/ Detay^ AVC """ob* 6 Zv<f * i Delay Level Signal y c (b) Figure 14.7 (a) An AVC circuit; (b) automatic volume control action. The Single-Sideband System of Modulation measure of received signal strength that is used to achieve automatic volume '"shovvn^lhe circuit in Fig. 14.7(a) is an * a C, filter at the diode detector nutoul The R Z C 2 product is made large, a fraction of a second, to remove °ny modulation at low/, frequencies from the dc voltage. Connected as 'shown, the output or D t makes this dc voltage negattve to ground After filtering, this dc voltage is applied to the base of the npn transistor Q t and other amplifier transistors, to reduce l E . Both h„ and h„ are functions of l s and the gain of the amplifiers can be reduced as the strength of the received signal increases, as measured by V c . ' Without AVC the output of the detector increases in proportion to the input signal as shown in Fig. 14.7(b). The AVC action decreases the gain with increased signal strength, giving an output change as shown by the dashed curve and holding all signals more nearly constant in output. All signal levels produce an AVC voltage, however, and the gain is reduced even for weak signals, where the full gain is needed. Accordingly we use delayed A VC, applied by the diode clamp circuit at point A on the AVC line of the amplifier. Until the AVC line reaches - V„, the delay toas diode D 2 is closed and transmits -V B volts on the AVC line; this is the des.red bias level for all amplifiers. But when the AVC voltage from D, becomes more negative than -V„, diode D t opens and the varying AVC bias is used to control the amplifier gain. The result is a high gain for weak signals and a more ideal AVC characteristic for large signals, as shown in Fig 14.7. 14.8 The Single-Sideband System of Modulation At 100 per cent modulation in an AM signal, the carrier requires two-thirds of the power but conveys no useful information. The carrier can be viewed as a power waste and the second sideband as needless duplication, except for its rare aid when selective fading distorts one sideband in radio transmission. If we use only one sideband and suppress the carrier, we have the system gener- ally known as single-sideband (SSB) transmission. We are able to transmit the information with reduced power requirements, half of the bandwidth and lessened interference between signals, but at some expense in complexity ot equipment. . A carrier must be introduced at the receiver, closely adjusted to the origi- nal carrier frequency since a A/ carrier difTcrence produces a A/ shift in all signal frequencies and introduces distortion. The carrier must be accurate to within 10 or 20 Hz for intelligibility of voice signals, and stable oscillators are required to generate the local carrier. The first step in generation of an SSB signal is to develop an AM signal 338 Modulation and Detection t" ih- 000 v2) 'Output (a) (b) flfeHK /<.* (a) A balanced modulator; (b) a diode balanced modulator. without carrier. A balanced modulator is used, as shown in Fig. 14.8(a). The respective inputs to Q, and Q z have the/, signal common and the/, signal differentially connected, giving v, = V c cos 2nf c t + V, cos 2nf,t (14.28) f j = K c cos 2nf e t - V, cos 2nf,t (14.29) The emitter-base junctions of the transistors can be assumed to have volt- age-current relations that can be represented by Eq. 14.15, as / = a,v f a 2 v z Use of Eq. 14.28 and 14.29 as the applied voltages produces mixing of the two frequencies; with the push-pull connection giving a subtractive output, the output expression will contain only the terms /. - 2a , V, cos 2nf,t -\ *a z V,V c cos 2nf,i cos 2tt/ c / (14.30) Now in Sec. 14.2 we used the trigonometric identity cos a cos b — $ cos (a -|- b) I J cos (a — b) Expanding the product term of Eq. 14.30 according to this relation, we have /„ = 2a, V, cos Infjt + 2a 2 K,K c [cos 2n(f e +f,)t | cos 2n(f c - f,)t] The output circuit is parallel resonant and of high resistance R p only near frequency/,. Frequency/ </ c by assumption and the first term does not produce an appreciable voltage across the circuit because the circuit imped- ance is negligible at/,. Thus, with R p as the resonant impedance, the vojtage across the output circuit is only v = 2o 2 fl ; ,K 1 |/ c [cos 2n(f c +f,)t ■ cos 2n(f c - f,)t) (14.31) where f t +/, and / - / represent the sidebands of an AM wave and with Frequency Translation; the Product Detector 339 the carrier absent. This result should not be surprising since the carrier rep- resented a common input to the two transistors, in push-pull or differential connection. Another form of balanced modulator is shown in Fig. 14.8(b), using diodes instead of transistors. The action of the circuit is similar to that of the transistor circuit and the output consists solely of the two sideband frequen- cies. The circuit is commonly used in telephone carrier-current transmission and requires accurate center-tap connections on the transformers for balanc- ing out the carrier. The sideband outputs are shown schematically in Fig. 14.9(a). A sharp cutoff filter must be used to select one of the sidebands, yielding the SSB signal in Fig. 14.9(b). The filter must separate signals in the two sidebands that differ only by twice the lowest modulation frequency. For voice frequen- cies the amplifiers arc usually designed to cut off at about 200 Hz so that the lowest frequencies will differ by at least 400 Hz, as indicated by the separation of the bands in Fig. 14.9(a). Filters that can achieve this amount of skirt selectivity and place the rejected sideband at least 30 dB below the level of the accepted frequencies are usually designed with piezoelectric quartz ele- ments of high Q and operate at/ c frequencies of 2 to 5 MHz. (a) (b) Figure 14.9 (a) Balanced modulator output spectra; (b) output after lower sideband is removed by filtering. 14.9 Frequency Translation ; the Product Detector By use of the principle of modulation it is possible to translate a band of frequencies centering at f„ to a band of similar frequencies centering at an- other frequency f b . As for modulation, an input signal of frequency f e and a locally generated signal at /, are simultaneously applied to a diode, tran- sistor, or tube having a parabolic characteristic to produce the frequency- product term necessary for modulation. An output voltage then appears in a circuit tuned to/ e ±f x - 340 Modulation and Detection The signal to be translated may be an AM wave, having a carrier/ and side frequencies at A -\- f, and/ — /,. The translation process yields sums and differences of all input frequencies and if we mix a local signal at fre- quency/,, we shall have the following output frequencies: /. A f. I- /.-/, A-A=A f. I A + A =/, + A A +/. ~f„ - A +/, /. -/. i- A -A -A A -A -A -A -A The sum and difference terms will have amplitudes proportional to the products of the individual wave amplitudes. The frequency groups centered at A and A constitute two translated AM waves, each containing the original side frequencies but moved up and down onto new carrier frequencies. This principle of frequency translation receives wide application in receivers and transmitters. Additional frequencies of small amplitude are generated in the process. These spurious frequencies can create interference signals in other channels unless suppressed by high-g resonant filters. The translator in Fig. 14.10 employs one transistor for local generation of A and the mixing of the frequencies. The resonant circuit of L x , C x and the feedback coil L M form an emitter-tuned oscillator operating at f x . The internal interaction through the base-emitter junction with f. produces an output in the L k , C k circuit tuned to/. The A output is predicted by a con- version transconcluctance g c and the conversion gain is A c - g c R (14.32) where R is the resonant resistance of the output circuit at frequency/. The circuit is useful as a translator even if A c is less than unity. The process of frequency translation is also employed in the product detector by which we reinsert the carrier and recover the SSB signals. Suppose that the input at/ in Fig. 14.10(b) is modulated as an upper sideband/ + /• Then suppose that the locally generated oscillation is adjusted to f x /].. The mixed output will include frequencies at A A+A A +A +/. A -t-A -A -/. The first three output frequencies are high and are bypassed by C but the last frequency at A ' s tna t of the original modulation; it is passed to the output through C c . This is the method for reintroduction of the carrier, and for good intelli- gibility the local oscillation must be within 10 or 20 Hz of the/ used in gen- erating the transmitted sideband. Severe requirements are seen to be placed on the stability of the local oscillator. The Frequency Spectrum of FM Signals 341 (a) ■f [ Audio Outpul Figure 14.10 (a) Transistor frequency translator; (b) product detector. 14. 10 The Frequency Spectrum of FM Signals Most natural and man-made radio noise is in the form of amplitude variations of the signal and a system that eliminates amplitude variation in its received signals can also eliminate most radio noise. The system of frequency modula- tion operates with constant amplitude signals and is effective in reducing noise in radio reception. If we are to design circuits for FM equipment, we must know the fre- quency spectrum required by the frequency components of a frequency- modulated (FM) wave. We shall again use as the information to be transmitted a frequency/ and a signal voltage v, = V, cos Inf.t (14.33) We vary the frequency of our FM wave in proportion to the amplitude of this signal. We define the frequency deviation as ft**kfV t (kHz) (14.34) 342 Modulation and Detection where k, is the proportionality factor in kilohertz per volt. This relates the amplitude of the modulating signal to the frequency variation of the FM wave. Suppose that a 1-V signal produces a IO-kHz deviation, then k f = 10 kHz/V. This is applied to a 50-MHz frequency and the frequency is shifted to 50.01 MHz. A 2-V signal produces a 20-kHz deviation to 50.02 MHz; a — 2-V signal swings the frequency to 49.98 MHz. If the frequency / is 1000 Hz, then the swings between 50.02 and 49.98 MHz occur 1000 times per second for a 2-V peak cosine signal. Maximum values of/, are assigned for various radio services, as 75 kHz for sound broadcasting and 25 kHz for the sound channel in television. Maximum signal frequencies are/, (ra ,„ = 15 kHz for the audio range. Then we define the deviation ratio as Jilniil /i(mtx) (14.35) Thus m, ■= 75 kHz/15 kHz — 5 for sound broadcasting. With modulation by the signal of Eq. 14.33, our FM wave can be written as v = V a cos (2a/,/ -i- m f sin 2a/,/) (14.36) The frequency/, is called the center frequency because the FM signal deviates up and down from the/ value, in accordance with the modulation term in the parentheses. The center frequency may go to zero for some values of m s and this is the reason we do not call / a carrier frequency. There are side frequencies in pairs above and below the center frequency at every harmonic of/ all the way to infinite frequency. The side frequencies are not restricted to ±Z as for AM. Practically, we do not have to contend with FM signals of infinite band- width. The amplitudes of the high-order side frequencies decrease quite rapidly and become negligible; however, we do use bandwidths of ±75 kHz for FM sound broadcasting. The wider bandwidths give greater suppression of noise in FM transmission through space. 14. 1 1 Bandwidth of FM Signals The necessary FM bandwidth for good waveform reproduction can be assumed as BW ~ 2/ (n ,„, (14.37) Spectrum frequencies and amplitudes for an unmodulated amplitude of unity are plotted in Fig. 14.11 for a variety of signal and m, conditions; all components with amplitudes over 1 per cent are shown. 0.76 ./> ./> L J •fd-* -Id- \L. ^1 (a) f d = 5 kHz /, =5 kHz in, = 1.0 (b) l a = 25 kHz /, =5 kiiz m, - S.O f d =50 kHz /, = 5 kHz m, = 1 0.0 M) r« = 75 kHz A ■ 5 kHz '"/ = 15.0 Lu — 75 kHz — -\- 75 kHz— /„ Figure 14.11 Spectra of FM waves for various m f values. 343 344 Modulation and Detection In FM broadcasting, f i{m , x) has been established at 175 kHz and the usual design makes the receiver bandwidth ± 100 kHz, which accommodates all side frequencies that arc greater than 1 per cent in amplitude, according to Fig. 14.11(d). Since the amplitude V B is unchanged by frequency modulation, the average powers in unmodulated and modulated waves are equal. Modulation simply spreads the available energy among the sidebands. The spectrum for m f — 1.0, shown in Fig. 14.1 1(a), closely approaches that of an AM wave and it is found that for m f = 0.6 or less the spectrum reduces to v„ = V B [A„ cos 2nfj + A , cos 2n(f„ + /,)/ - A , cos 2n(f - f,)t] (14.38) which is similar to double-sideband AM. The bandwidth is then bw = y JtaMj and the system is said to be one of narrow-band FM. For m f > 0.6, the system is considered wide-band in nature. 14. 12 Generation of FM Signals An FM signal may be generated by causing the capacitance of a tuned-circuit oscillator to vary with the modulating signal amplitude. A semiconductor diode may be connected across the tuned circuit, with the diode under reversed bias. The capacitance of the junction will vary if a bias voltage »* — - V BO I V, cos 2nf,t (14.39) is applied. With the capacitance of the diode proportional to the squaie root of the applied voltage, the amplitude of V, must be kept small for linearity. But with V, small, the frequency of the oscillator will be and this conforms to the needs for FM generation. (14.40) 14. 13 The Limiter and Discriminator for FM Detection Noise and varying amplitude interference may arrive with the FM signals. Since FM signals have constant amplitude, this interference may be removed by limiting all signals to a common amplitude. With this done, the only vary- ing property of the input is frequency and we can proceed to convert the V The Limiter and Discriminator for FM Detection 345 frequency variations back to the amplitude variations of the original speech or music. One form of amplitude limiter employs an amplifier with low collector voltage so that the load line of the transistor is short and all incoming signals arc large enough to drive the amplifier to cutoff and to saturation. Since this distance on the load line is fixed, all signals above a threshold value will ap- pear at a uniform output level; this is illustrated in Fig. 14.12(a). -<s -»: -Useful Range- Noisc Output 10 20 30 Limiter Input (V) 40 0.8 0.6 0.4 s? 0.2 1 u' 0.2 -0.4 0.6 0.8 (a) 200 - 100 100 200 k'.:/ Deviation at 10 MHz (b) Figure 14.12 (a) Limiter performance; (b) discriminator action. Another circuit that adopts operational amplifier construction is shown in Fig. 14.13(a). The transistors arc normally biased into equal conduction. For any input V, more negative than some value -V x , g, is cut off and the bias from R E is reduced because of the smaller common current. This reduc- tion in bias raises the current in Q 2 and its output voltage becomes V, u . Then as V, rises, Q x begins to conduct and the emitter voltage rises, reducing the current in Q x . At some positive V, = +V X on Q„ the bias across R B becomes large enough to cut off Q x and its output voltage goes to V cc . For any input signal with peak-to-peak amplitude exceeding 2V„, the output is limited at a peak-to-peak value of V^ - V m . This action is demon- strated in Fig. 14.13(b). The Foster-Seeley discriminator shown in Fig. 14.14 is one form of detec- tor for FM signals. The input transformer serves as a load for a limiter circuit and the primary voltage is in scries with the secondary voltage to ground, the reactance of the blocking capacitor C being neglected. The diodes D„ and D b have applied voltages (14.41) V„ = V x + % -V -£ The primary and secondary voltages of the overcoupled circuit, at a 346 Modulation and Detection v G, ore (a) (b) Figure 14.13 An emitter-coupled limiler. 2 Limiter Discriniinutor Figure 14.14 A frequency discriminator. resonant frequency equal to the FM center frequency, are (14.42) (14.43) The./ factor in V z shows it to be in phase quadrature to V x . Thus we draw the phasor diagram in Fig. 14.15(a) with V, and K 2 at right angles at resonance. Diode voltages V a and V„ are shown as the sum and difference of K, and V x \2 according to Eq. 14.41. At frequencies below resonance the phase of K 2 changes toward the diagram in Fig. 14.15(b) and above resonance the phase of V t shifts oppositely toward the diagram in Fig. 14.15(c). The diodes provide an output equal to V„ — V b and at resonance this is The Ratio Detector for FM 347 2 (a) (b) (c) Figure 14.15 Phasor description of discriminator performance. zero. At deviations above and below resonance the angle 9 becomes smaller and larger, respectively, and the difference V a — V b progressively changes. This voltage difference is translated into the diode output curve in Fig. 14.12(b). Linear output voltage versus frequency is available for a range of nearly ±150 kHz at a center frequency of 10 MHz. Equation 14.42 shows that the output is proportional to the input ampli- tude K„; thus the output would vary with amplitude or noise if the circuit were not preceded by a limiter. The transformer is overcoupled and the separation of the response peaks in Fig. 14.12(b) is dependent on the Q of the primary and secondary circuits. With Q t = Q 2 — Q, the needed value is = L 2/,J(m.i) For speech and music 2f dla , x) = 200 kHz and at/ = 10 MHz, the value of Q will be 50. 14. 14 The Ratio Detector for FM Another detector for FM is the ratio detector drawn in Fig. 14.16. The full secondary voltage charges C c to the peak of signal V, through the two diodes in series. The values of R 2 and C c are large so that V is constant for a given signal but varies for different signal amplitudes. As in the discriminator, the primary voltage and one-half of the secondary voltage is applied to each diode. At the center frequency these voltages are equal and there is equal charge in C, and C 2 but there is no voltage across /?,. This is true regardless of the magnitudes of V a and V b . When frequency deviations occur, the unequal diode voltages charge C, and C 2 unequally but the total of V„ and V b is constant at V. Voltage at A is dependent on the proportional change in V a and V b and so we have the ratio detector. A varying signal then appears at A to ground. 348 Modulation and Detection Figure 14.16 The ralio detector. The performance of the circuit is somewhat affected by signal amplitude and the operation is improved if the circuit is preceded by a limitcr. 14. 15 Automatic Frequency Control (AFC) At the high frequencies employed with FM a crystal cannot always be used and automatic frequency controI(AFC) circuits are used to improve frequency stability. A discriminator circuit is connected to the oscillator output as in Fig. 14.17. When the oscillator frequency corresponds to the center frequency for which the discriminator is tuned, the output from the discriminator is zero. When the oscillator is off frequency, a positive or negative voltage is devel- oped at the discriminator output. This voltage is filtered to remove signal components and applied to a reverse-biased diode capacitor across the oscil- lator tuned circuit, where the voltage adds or subtracts to a fixed reverse bias. A bias change in one direction causes an increase in diode capacitance and a reduction of oscillator frequency; a bias change in the opposite direction causes a reduction in diode capacitance and an increase in oscillator frequency. Biased Oscillator Amplifier » Output al/„ Diode Filter Figure 14.17 Automatic frequency control (AFC). Review Questions 349 The directional bias from the discriminator is always so polarized as to shift the oscillator frequency toward its proper frequency. FM receivers are stabilized against frequency drift with temperature by such circuits. 14.16 Comments The transmission of information by radio waves requires that those waves be controlled by the informational signal. We can vary any one of three charac- teristics of the radio wave, its amplitude in AM, its frequency in FM, and its phase in PM. Thus low-frequency audio and picture signals can be transferred to a higher frequency, which will radiate efficiently through space. AM involves simple equipment but is susceptible to noise and interference. The SSB-AM system is most economical in its use of frequency space. FM requires more complex equipment and employs wide frequency bands but noise interference does not limit its usefulness. For equally intelligible signals, SSB-AM and FM use much less power than does the AM system. Thus there is no one system that is better than the others for all purposes but we can say that double-sideband AM is generally less useful than the other systems and its application is declining. The process of frequency translation to different frequency bands is employed in receivers as well as in transmitters and requires the development of the product of two frequencies. The output always contains more fre- quencies that does the input, sometimes a great many more. Tuned circuit filters are ordinarily used to separate the wanted frequencies from the ones not wanted. REVIEW QUESTIONS 14.1 What are two fundamental methods of modulating a wave of frequency /? 14.2 What is the process of amplitude modulation? 14.3 What is the process of FM ? 14.4 What is PM ? 14.5 What are the types of pulse modulation? 14.6 What is the modulation factor in AM ? 14.7 Sketch an AM wave as modulated by a square wave. 14.8 Sketch an FM wave as modulated by a square wave. 14.9 Why is the bandwidth of an AM signal twice the highest frequency present in the modulating signals? 14.10 What are upper and lower sidebands of an AM wave? How are their fre- quencies related to the modulating signal? 350 Modulation and Detection 14.11 What is the relation of carrier power to sideband power at 50 per cent modu- lation? At 100 per cent modulation? 14.12 Why do wc filter the output of a diode modulator? 14.13 At m a = 1.0, what carrier power must be supplied if the modulator output is 750 W? What is the power in the upper sideband? 14.14 A broadcast station is assigned a carrier frequency of 990 kHz and a band- width of 10 kHz. What range of frequencies can it transmit in the sidebands? 14.15 What is per cent modulation in AM? 14.16 What is meant by SSB? By DSB? 14.17 For the same power in the information signal, compare the total power in AM-DSB and in SSB. 14.18 How is an SSB signal generated? 14.19 Compare DSB-AM and SSB on the basis of bandwidth. 14.20 Explain the operation of a diode detector. 14.21 What is frequency translation? 14.22 Explain a product detector. When is it used? 14.23 What is the most serious problem in SSB reception? 14.24 What is meant by AVC? Describe AVC circuit performance. 14.25 What is delayed AVC and why is it used? 14.26 What is the purpose of a balanced modulator? 14.27 What is frequency deviation in FM ? 14.28 Compare AM and FM on bandwidth needs. 14.29 Why does the power in an FM wave not vary? 14.30 What is the approximate bandwidth of an FM signal? 14.31 An FM signal has a deviation of 90 kHz for a • 10-V signal. What is the value of k,l 14.32 An FM station has a channel from 90.8 to 91 MHz. (a) What is its center frequency ? (b) What is the maximum permissible deviation ratio for a max modulating frequency of 10 kHz? 14.33 What is a limitcr? Why is it needed in FM reception? 14.34 Explain one form of limitcr circuit. 14.35 Explain the action of a discriminator. 14.36 A diode modulator has input frequencies at 2.75, 2.80, and 2.95 MHz. The mixing frequency is 2.345 MHz. What output frequencies arc obtained? 14.37 Explain how to translate a frequency from 30 MHz to 1.65 MHz; give fre- quencies involved in the output and explain their separation. 14.38 What is narrow-band FM? Problems 361 14.39 What is wide-band FM ? What is its advantage over AM in a noisy channel ? 14.40 How can per cent AM be found from an oscilloscope pattern? 14.41 What is AFC? PROBLEMS 14.1 The carrier of an AM wave is at 25 W. What is the average power in each sideband at 40 per cent modulation ? 14.2 A carrier is generated at 150 W and the average modulator power output is 45 W. What per cent modulation is possible? 14.3 An AM wave is stated by v = 100[l + 0.20 cos 271(1000)/ + 0.05 cos 2n(3000)r] cos 10 6 / State all frequencies present in hertz, and give the per cent modulation for each. 14.4 A modulated amplifier operates at 2250 V and a carrier power input of 500 W. (a) What modulator power output will be required for 80 per cent modula- tion? (b) What is the ratio needed for the Class B output transformer for the modu- lator if the Class B stage needs a 7500-Ji output primary load? 14.5 An AM transmitter has a carrier or 1000 W. What average output must the modulator have to reach 80 per cent modulation? What is the total average power required by the wave? 14.6 In Problem 14.5, what would be the per cent saving in power if the same information was transmitted by SSB? 14.7 An AM carrier is at/, - 10 kHz and is modulated 50 per cent by f„ --= 400 Hz and 20 per cent by A 800 Hz. Plot a frequency spectrum showing proper amplitudes if the carrier is shown at 2.5-cm length. 14.8 If the carrier in Problem 14.7 is at 100 W, what is the total power in the AM wave? 14.9 The current in a diode modulator is given by mA, / =- 10 ( 2.5i; + 1 .Or 2 The voltage applied to the modulator is v = [3.0 cos 271(60,000)/ • 0.2 cos 27t(IOOO)/] Calculate the amplitude and frequency of all output current components. 14.10 A carrier of an AM wave has V c - 2.75 V at the detector. What voltage is available for AVC action? If m a - 0.5, find the voltage of the audio signal at the detector output. 14.11 A 100-kHz carrier is amplitude modulated by a 5-kHz signal and the upper 362 Modulation and Detection sideband is transmitted. The receiver mixes a signal of 100.3 kHz. What is the frequency of the recovered audio signal? Has distortion occurred? 14.12 An SSB signal f c +f, is applied to a frequency translator along with V, sin 2n/,t. Show that the SSB signal may be translated to a higher frequency or a lower frequency without distortion of the side frequencies. 14.13 A 10,000-Hz modulating signal gives m f = 15 in an FM transmitter. What is the minimum desirable bandwidth for the transmitter resonant circuits? 14.14 In an FM transmitter, when the audio frequency is 400 Hz and the audio voltage is 2.5 V, the deviation of frequency is 5.7 kHz. What audio voltage will cause a deviation of 10 kHz? 14.15 If the maximum audio frequency applied to an FM transmitter is 5.0 kHz and m f = 20, what is the maximum frequency deviation from 10 MHz? 14.16 A steady carrier at 4.350 MHz is transmitted adjacent to one on 4.354 MHz, modulated at 2000 Hz. What output frequencies arc found in a remote receiver? Do you see any problems arising? 14.17 An FM signal has a maximum frequency deviation of 50 kHz and is modu- lated by audio signals up to a maximum of 10 kHz. If a receiver has a band- width of 50 kHz, is this adequate? 14.18 An FM station with/ l(m „, -^ 15kHzandm/ = 7operatesat 10-MHzcenter frequency. What should be the — 3-dB bandwidth of a tuned circuit to pass the major spectrum components of this signal ? What Q would be required of the resonant circuit ? 14.19 An FM system uses 15 MHz as a center frequency. The modulating signal when at 10 kHz generates a maximum frequency deviation of 5 kHz. Find the bandwidth to pass the necessary components for good fidelity of the received signal. 15 Radio Systems Radio systems are designed to transmit information and the noise appearing along the transmission path is the basic low-signal limit for reception. We now have sufficient knowledge of circuits and the basic processes of modu- lation and detection to understand the overall design of radio receivers and transmitters and can discuss some of the system considerations that include noise, bandwidth of signal, power, and method of modulation. As in most engineering problems, there is rarely a unique answer to be found and trade-offs are necessary. 15.1 Noise Random variations of current in electronic circuits are called noise. External noise caused by atmospheric discharges or static limits radio reception of weak signals below about 20 MHz. At higher frequencies the external noise decreases and random currents internal to the circuits produce a noise or hiss and this limits weak signal reception. Circuit noise is predominantly due to impacts of electrons and atoms in thermal agitation in the materials of the circuits. Each impact sends out a short energy pulse with a very broad frequency range. The thermal noise produced by a resistance R (an antenna, for example) appears as the voltage of an equivalent noise generator K, olM = 7.4 X 10-' VTOW) (15.1) 353 364 Radio Systems where T= temperature, degrees absolute (°C + 273°) R = resistance of the circuit BW ^ frequency band (3-dB) included in the noise measurement For a resistance of 100 £1 at room temperature (300° absolute), the noise voltage is 1.28 //V per MHz of bandwidth. Since the noise is dependent on temperature, when receiving very weak space signals the input stages are sometimes immersed in a case at the temperature of liquid helium. This reduces T in Eq. 15.1 and therefore the circuit noise. A weaker signal can then be received. The amount by which the signal power overrides the noise power in the circuit determines the understandability of the signal and we speak of signal-to-noise ratio in evaluating circuit performance. The noise contributed by an amplifier is measured by the noise figure (N.F.), stated as the ratio of the signal power to noise power at the input, SJ N„ to the same ratio at the output, SJN„. That is, KF.-!fjg (15.2) The measurement is usually expressed in decibels. The amplifier noise added in the circuit degrades the signal, making SJN less than S,/N,. Some tran- sistors arc less noisy than others and less noise is usually produced when the transistor is operated at low currents and voltages. Noise figure for input stages at high frequencies is usually in the range of 4 to 6 dB, although 2 to 3 dB can be obtained by careful transistor selection. 15.2 Information in Signals We now need a measurement of the information contained in a signal. In a pulsed data transmission system we need to recognize only two levels of output per pulse interval: on and off. The quantity of information is assumed to depend on the number of such levels or conditions that we must recognize in a unit signal; that is, /„ = log 2 L bits (15.3) where /„ is the number of Ms (basic units of signal), L is the number of recog- nizable levels or signal conditions, and the logarithmic base of 2 results from the fact that each signal level has an even probability of being recorded correctly or incorrectly. Admittedly this is an arbitrary definition but it leads to useful and comparative results. The single pulse is our unit of information content since with L ^ 2, on and off, then /„ = log 2 2=1 bit Information Capacity ot a Channel 35S If we transmit 500,000 pulses per second, each I //s long, the rate of informa- tion is high, as R - 500,000 bits/s With a pulse length of 1 /is, the bandwidth must be I MHz for reasonable accuracy of waveform in this data system. Speech is our most usual form of information transmittal. With speech we can encompass a range of 1000 : 1, or 30 dB, between the weakest intelligible sound and the loudest sound in the human voice. It takes an intensity change of about 2.5 dB before the ear can notice a change of intensity; with an intensity range of 30 dB, we are able to recognize 12 significant levels of speech intensity. Thus L = 12 for speech. While speech contains frequencies up to about 6000 Hz, good intelligibility is possible with the channel narrowed to 3000 Hz, as in the telephone. The basic interval in speech is considered to be a half cycle of the highest frequency present, or 6000 intervals per second for a 3000-Hz speech transmission. With 12 recognizable intensity levels in speech, the maximum information rate in speech is R = 6000 log 2 12 = 2000 x 3.58 = 20,500 bits/s Channel bandwidth is, of course, 3000 Hz. A television signal can be similarly analyzed. The difference between white and black on a television screen is not very great and the eye can only distinguish about 10 levels of gray between the black and white limits. The picture is formed in dots on horizontal lines and the eye can resolve about 500 dots of white, black, or color per line. In the United States television system there are 525 lines per picture and 30 pictures or frames per second. Putting this data together, we can calculate the information rate in a television signal as R = 500 X 525 x 30 log 2 10 = 2.62 x 10 7 bits/s We see that the speech rate of 20,500 bits/s is low but only requires a bandwidth of 3000 Hz. Data pulses transmit information at 500,000 bits/s or more and require a few megahertz of bandwidth. Television transmits infor- mation at very high rates and utilizes 4.5 MHz of bandwidth. Thus we conclude that the bandwidth occupied by a signal is proportional to the rate at which information is transmitted. 15.3 Information Capacity of a Channel We now need to measure the information capacity of a transmission channel. The more levels we try to separate, the smaller are the differences between signal levels and the lower is the accuracy of discrimination in the presence of 356 Radio Systems noise. A quiet channel will have a greater information capacity than a noisy one and to measure the information capacity of a channel we use the signal- to-noise ratio. Suppose we have a given bandwidth and a received signal power S and noise power A'. The power input to the receiver is S + N in the presence of N units of noise power. The number of distinguishable levels of signal is assumed to increase as the ratio of voltages or W s -^=V'+# (1S.4) since a voltage V is proportional to ,/ Power. The information received through the channel per basic signal interval is /. = log 2A /l+^ = 4-lo gi (l ! --£) (15.S) The number of basic intervals per second is the rate of sampling, or twice the bandwidth. The information rate is 1 /? = 2Bx4-log 2 (l-|) The total information that can be transmitted over a noisy channel in total time T is C=5riog 2 (l I -£-) bits (15.6) 4.U 3.5 s s ^^— 1 f\ s ' J.U c *> < 1 -■■» J.O i 1.5 / 1.0 I 12 14 16 8 10 x Figure IS. I Logarithms to the base 2. An AM Transmitter 357 This is known as the Hartley-Shannon law. For its use we provide a curve of logarithms to the base 2 in Fig. 15.1. The received signal may be partially masked by some noise, and the received message will be inaccurate. This means that the S/N ratio is low and the channel capacity is reduced. The channel capacity for accurate reception of a signal can be increased by widening the bandwidth B, as by use of FM or by use of a pulse-code system. The time T taken to transmit a message can also be increased, possibly by sending a message twice or repeating parts of it as is done in some data transmission systems. An increase in channel capacity can be accom- plished by raising the transmitter power, giving a larger S/N ratio at the receiver. This method is expensive, however, because S/N appears in the logarithm term and an increase of power by about 10 is needed to make a useful improvement. A cheaper means of improving S/N is often found by use of a more effective antenna system, using directional gain for the signal and having some directional discrimination against the noise sources. Figure 15.2 Block diagram for an AM transmitter. 75.4 An AM Transmitter A block diagram of an AM transmitter is shown in Fig. 15.2. A submultiple of the output frequency is usually generated by the oscillator since lower- frequency crystals are more stable. A buffer amplifier is used to isolate the oscillator circuit from variations in the remainder of the transmitter, improving the oscillator frequency stability. The oscillator frequency is then multiplied by frequency doublers or triplers. These are overbiased amplifiers 1 358 Radio Systems with loads luned to twice or three times the input frequency. In addition to frequency multiplication, these amplifiers increase the power level sufficiently to drive the modulated amplifier. An audio amplifier is driven by the microphone signal at frequencies f t and raises the power level sufficiently to drive the Class B modulator to full output. The output power for the sidebands is transferred through the modulation transformer to the modulated amplifier. This transformer has a turns ratio that will produce the desired load for the Class B amplifier and transfer the power to the secondary load represented by the resistance of the modulated amplifier V cc jl c . Power modulation is obtained and the modulated signals arc coupled to the antenna through the it network, which is designed to transform the large load value of the amplifier to the 50 or 75 fi that the antenna represents. At the same time the n network acts as a filter and removes extraneous harmonics from the amplifier output. An AM transmitter has simple circuits and is easy to adjust for modula- tion without distortion. Amplitude-modulated signals use a carrier that transmits no useful information, however, and can be considered to be a waste of power; AM signals also require a bandwidth that is twice the modu- lating signal band. More importantly, perhaps, AM suffers from heterodyne interference, created when another carrier is within a few kilohertz so that their difference or beat frequency produces a steady audio whistle in the output of the receiver. The use of AM is declining because of heterodyne interference, its band- width requirements, sensitivity to noise, and its power requirement. 15.5 The Superheterodyne Receiver Reception of AM signals is done with the superheterodyne receiver, shown in block form in Fig. 15.3(a). The incoming signal has a carrier frequency/., with sidebands at/ +/, and/. — /„ where/, is the audio or information signal. This AM signal is translated to a new frequency band, with carrier frequency f k and sidebands at/* i/„ by mixing with the first oscillator. The oscillator frequency is/ x and that frequency is adjusted so that/, = /,+/* for all incoming signals to which the receiver is tuned; that is,/, is made to vary in step with /. Ampli- fication follows at/*, the intermediate frequency (I.F.), in an amplifier with fixed tuning at/*. Since the intermediate frequency is usually lower than the frequency of the input signal, the tuned circuits in the l.F. amplifier can have more selectivity (in terms of bandwidth in hertz) than can be obtained with simple parallel-resonant circuits at the incoming radio frequency. The l.F. circuits employ double-tuned transformers that give a flat top and steep The Superheterodyne Receiver 7 Signal Ciain Image Suppn»> sion i ' RF. Amplifier Translator " ft*f, u Oscillator Channel Selectivity \ l.F. Amplifier Detector h f, f, Audio Amplifier (a) Power Amplifier Ik'al Oscillator h = h l.F. Amplifier Product Detector h L h « Audio Power Amplifier Amplifier 4 (b) Figure 15.3 Block diagram of a superheterodyne receiver for AM signals; (b) demodulation of SSB-AM signals. skirts to the overall response curve. This flat response is made just wide enough to include all the sideband frequencies present in/* -| /, and/* — /,. After l.F. amplification the signal goes to the diode detector and the original modulation frequency /, is derived. Audio frequency and power amplification follow before the signal reaches the loudspeaker. There will always be unintentional positive feedback, introduced by common couplings in power supplies, by fields between connecting wires, or by stray capacitances. This positive feedback, although small, will limit the amount of gain possible at one frequency because when A becomes large, the 360 Radio Systems product Af) will approach — 1 and instability will occur. By shifting the frequency band it is possible to approach the limiting stable gain in each frequency band in succession. Thus high gain is an advantage of the super- heterodyne receiver. Because of the requirement of the superheterodyne system that the intermediate frequency f k be a constant for all received frequencies, the oscillator frequency /, must continuously differ from the frequency of the carrier/, by the amount of the I.F., i.e.,/ t . For any oscillator frequency, two signals can give an output to the intermediate frequency amplifier. These signals differ by 2f k , one being below/, at/, —f k ^f Cl and one above/, at / w | f k =/ ci . if the desired signal is at/ ci = 545 kHz and the I.F. is/,, = 455 kHz, then the oscillator must be tuned to/, =/., +f k = 1000 kHz. A second signal at f x | f„ = 1000 + 455 = 1455 kHz =/„ can also be received simultaneously and would be called the image frequency. By using sufficiently selective radio-frequency circuits in the R.F. ampli- fier, the strength of the undesired image signals can be lowered and it is possible to reduce greatly or to eliminate image responses. At signal fre- quencies of 20 MHz or more, however, an I.F. of 455 kHz places the image at only 20.910 MHz. The radio-frequency tuned circuits cannot give sufficient attenuation for a frequency so close to the desired carrier and images will be received with the desired signals. To eliminate images in such high-frequency receivers, a higher I.F. is used, possibly 5.5 MHz, so that for the 20-MHz signal the image frequency will be at 31 MHz and sufficiently separated from the desired signal to be rejected by the input tuned circuits. A second translation from 5.5 MHz to 455 kHz can be carried out so that the skirt selectivity of the 455-kHz I.F. amplifier is also obtained for the 20-MHz received signal. Thus the selectivity curve of the receiver is really that of the lower- frequency I.F. amplifier. This makes the receiver selectivity curve independent of the frequency range for which the receiver is designed. This is a second advantage of the superheterodyne form of receiver circuit. Single-sideband signals can be received in the same circuit if a second oscillator is added to reinsert the carrier frequency as shown in Fig. 15.3(b). If the I.F. is 455 kHz, then/, of the second oscillator should also be 455 kHz. A product detector is used and the low or difference output frequency chosen, giving an output frequency of 455 ±f t — 455 =/.. The plus or minus sign is used, depending on whether the upper or lower sideband is being received. The output of the detector is /,, the original modulating signal. The oscillator frequency f y must be stable within 10 or 20 Hz if intelligible speech is to be recovered. A receiver for the broadcast band is designed to tune over the frequency range from 600 to 1 600 kHz. This is a frequency range of 1 600/600 = 2.67 : 1 . The resonant frequency of a tuned circuit varies with \\«f~C for a constant The Superheterodyne Receiver 361 inductance L. Most variable air capacitors have a maximum capacitance about 10 times their minimum capacitance so that «f\Q = 3.16 : 1. This is about the usual tuning range for a variable capacitor. The broadcast band, requiring a tuning range of 2.67 : 1, can be satisfactorily covered with such a capacitor. A small variable capacitance is used in parallel to adjust the minimum capacitance and to obtain the exact ratio of maximum to minimum capacitance needed for the tuning range. For a superheterodyne receiver with the I.F at 455 kHz, the oscillator frequency must range between Signal Frequency 600 kHz 1600 kHz Oscillator Frequency 145 or 1055 kHz 1145 or 2055 kHz The required tuning ratio for the oscillator tuning capacitor would be cither 1145 = 7.9:1 or |°J= 1.94:1 145 1055 The usual air variable capacitor has a range from 35 to 350 pF, or 10 to 1. Such a variable capacitor could not tune over the wide-frequency range from 145 to 1 145 kHz. Therefore the oscillator is designed to tune from 1055 to 2055 kHz and the oscillator frequency is placed above the signal frequency, or/, =/ e +/». Because the oscillator tuning range will be only 1.94: 1 compared to 2.67 : 1 for the radio-frequency signal circuits, the oscillator tuning capacitor usually has a lower maximum capacitance. Since the signal frequency is the difference between the oscillator fre- quency and the I.F.,/, =/„—/*, the image frequency occurs at a signal frequency that is the sum of the oscillator frequency and the I.F., /„ = /, -\-f k , and we have Signal Frequency 600 kHz 1600 kHz Oscillator Frequency 1055 kHz 2055 kHz Image Frequency 1510 kHz 2510 kHz This places the range of possible image frequencies between 1510 and 2510 kHz, almost entirely outside the broadcast band and in a region where strong signals are not prevalent. Therefore the reception of an image signal is not usual, although a strong broadcast station near 1500 kHz may appear at tuned frequencies near 600 kHz. 382 Radio Systems 15.6 The SSB Transmitter A transmitter for SSB signals is more complex than the AM unit and one is shown in block form in Fig. I5.4. A radio frequency of perhaps 5 MHz,/,, and the audio signal/, are introduced to a balanced modulator and sideband pairs obtained without a carrier. A filter selects the upper or lower sideband to be transmitted and in a second translator this sideband signal is added to a carrier/, such that/, +/,+/»=/, +/,. or/, -/,+/»=/,-/, for the lower sideband. This gives a single-sideband signal at the frequency/, at which it will be transmitted. The Class B linear amplifier provides a power gain for this varying amplitude signal. The output of the amplifier is coupled to the antenna through the n network for harmonic filtering of the Class B output. A frequency of about 5 MHz is chosen for the first oscillator so that the sideband filler can adequately separate the upper and lower sidebands, which differ by only 300 or 400 Hz. Such filters are usually composed of quartz piezoelectric crystals with high-£? values for sharp cutoff. /, Audio Amplifier /. f, fa+f, or /c+/x Balanced Modulator Filter Mixer Class B Linear Amplifier [/, = 5 MHz First Oscillator ',. Second Oscillator Figure 15.4 Block diagram of an SSB transmitter. Single-sideband signals are being generally used for point-to-point telephone service, especially for frequency multiplex as in the radio relay service. Frequency multiplex is illustrated in Fig. 15.5, where eight separate speech channels are used to prepare eight lower sideband signals with carriers spaced every 5 kHz from 15 to 50 kHz. After being "stacked up'" in frequency as shown, the composite signal, with frequencies from 12 to 49.7 kHz, is used as a modulating signal for a single carrier at 4000 MHz to yield a signal capable of transmission by radio relay. At the receiver the composite signal is detected back to the original range of 12 to 49.7 kHz and the eight signals separated by filters. The proper An SSB Transceiver 363 300-3000 11/. Speech § 1 Balanced Modulator I 2.000-14,700 Hz 15.300-18.000 Hz Sideband Filler 12.000-14.700 Hz Oscillator 15.000 Hz 300-3000 Hz Speech # 2 Balanced Modulator 17.000-19.700 Hz Sidebanc 20,300-23,000 Hz Filter ! Oscillator 20.000 Hz r- I 7,000-19.700 Hz Other Similar Signals -J 22.000-24.700 Hz 27.000-29.700 Hz 32,000-34,700 Hz 37.000-39.700 Hz 42.000-t4.700 Hz. 47.000-49.700 Hz -One Channel Figure 15.5 Frequency-division multiplexing of eight voice channels. carriers for each channel are added in separate product detectors and the original speech signals recovered. 15.7 An SSB Transceiver The block diagram of Fig. 1 5.6 illustrates a combined transmitter-receiver or transceiver, a type now commonly employed for SSB at high frequencies. The same frequency is used for both transmitting and receiving and the transmit- ting path of signals is indicated by dashed lines in the diagram. Let us assume that we tune to an SSB signal of upper sideband, derived from a carrier at 7.2 MHz. The band of frequencies near 7.2 MHz is amplified and mixed with a fixed oscillator operating at ll MHz. The difference frequencies are in a band near 4 MHz, including the desired signal, now at ► I! 2: T i c § 03 (/i V) c < •?. L ■n S° c/5 p: I N ■a 2 O £1 ™ V* o o- u (J c </: « c w ■a a u 13 -a Lu n 5 o o 2 w» .S«5 If < E < n. E 391 ,4n SSB Transmitter 365 II — 7.2 = 3.8 MHz. This band is mixed with the output of a variable- frequency oscillator, tunable over a 500-kHz range from 9.5 to 10 MHz. When the oscillator is set at 9.8 MHz, our desired signal will produce dif- ference frequencies close to 9.8 — 3.8 = 6.0 MHz. Only our sideband signal can pass through the filter with a narrow passband of about 2.5 kHz at 6.0 MHz, as shown in Fig. 15.7. All other signals in the original narrow band selected by the radio-frequency tuner arc removed here by the filter. An I.F. amplifier provides gain for the 6.0-MHz signal, which is then applied to the product detector. Here a 6.0-MHz carrier is reinserted and the speech frequencies/, are obtained as output. In the transmit mode the speech signal /, passes through the speech amplifier to a balanced modulator, where a 6-MHz signal is supplied from either of two carrier oscillators. These differ slightly in frequency so that the selected sideband will be centered in the passband of the same filter used for receiving at 6.0 MHz + 2.5 kHz. The signal at 6 MHz is mixed with the variable-frequency oscillator output at 9.8 MHz, giving a 3.8-MHz output. r^\ -6 i it - ■/*- -2.6 kHz- A lu in e I -30 E g - 1 tu 1 SCi 3U 60 4 t.9klly 1 (..000 6.001 6.002 MHz 6.003 Figure 15.7 Selectivity characteristics of 6-MHz sideband filter; 60dB,'6dB shape factor = 4.9/2.6 = 1.9. 366 Radio Systems A second mixing with the 1 1 -MHz oscillator frequency gives a difference frequency at 7.2 MHz, actually the same frequency as originally received. Power amplification with a driver and power amplifier operating in Class B follows. Advantages of SSB transceiver operation include 1. Only a single channel is used for transmission and reception. 2. SSB gives a narrow bandwidth equal to that of the modulating signal. 3. The transceive mode employs less expensive equipment, especially the filter. 4. The power required is only that of one sideband of an AM signal. The complexity of the equipment is the offset to these advantages. 15.8 AM versus FM For an AM signal the bandwidth is fixed. The rate of transmittal of informa- tion can be improved by increasing the transmitter power to raise the SjN ratio but this is expensive. With an FM signal, the bandwidth can be increased arbitrarily by increasing m f , assuming that frequencies are available. We can then receive a useful signal with a reduced S/N ratio. For instance, the total signal power in a 1 00 per cent modulated AM wave might be 150 W, while the power in an FM wave carrying the same informa- tion need be only that of one AM sideband or 25 W. The bandwidths might be 10 and lOO kHz, respectively. It is found that the information capacity or the usability of the FM channel is nine times greater than that of the AM channel; in fact, the FM system is superior as long as the 2/, value is greater than 10 kHz, the bandwidth of the AM signal. Since the power in an FM wave is constant, there need be no provision for the large instantaneous power and voltage peaks of an AM transmitter. The FM equipment can be smaller and cheaper. Noise signals caused by atmospheric static or man-made electrical discharges create reception problems for radio signals. In AM these noise signals may override the wanted signal and they cannot be separated. The noise can be reduced by narrowing the reception bandwidth but the minimum bandwidth of AM signals is determined by the modulating frequencies of the signal. If a receiver is designed for reception of wide-band FM signals and made insensitive to amplitude-varying noise by use of a limitcr, the noise can be largely eliminated. Interference between two signals on the same frequency is a major problem in radio communication. In AM, if the two signals have carriers differing FM Systems 367 only a few kilohcrtz, the difference appears as heterodyne interference, or a steady whistle in the receiver output. This is a frequent occurrence in the crowded AM bands. When this type of interference occurs between the higher-order sidebands of two AM broadcast stations with carrier frequencies spaced 10 kHz apart, the resultant noise is called "monkey chatter." Filters are often added to AM receivers to eliminate this form of interference. When two FM signals arc on the same center frequency, we encounter the capture effect, by which the stronger signal captures the receiver and blocks reception of any signal significantly weaker. Wider frequency devia- tion makes this capture effect greater. E.H. Armstrong was the first to demonstrate the value of FM in combating interference. Thus FM has a number of advantages over AM, particularly where noisy channels must be used with weak signals as in the mobile service and where power input must be limited. 15.9 FM Systems The FM transmitter diagrammed in Fig. 15.8 employs a variable-capacitance diode to shift the frequency of an oscillator in accordance with the modu- lation signal. The varying oscillator frequency may be generated with a center frequency of/, at which a suitable frequency deviation can be obtained. That varying frequency is translated by the output of a second oscillator at /», such that/, +f k =/,, where/, is the assigned output frequency of the transmitter. The side frequencies are then clustered around /, in the same manner that they were originally generated around/,. The power amplifier provides the antenna power at/, and side frequencies. f, I t.*h m f. Oscillator U Frequency Translator Power /. Uioui" Amplifier V Second Oscillator Varying DC Frequency Discriminator Figure 15.8 A reactance-modulated FM transmitter. 368 Radio Systems The output is also applied to the tuned circuit of the frequency discrimi- nator of Sec. 14.13, which yields a voltage as a measure of the average drift of frequency from the assigned channel at/,. If the frequency is not at normal, a correction voltage from the discriminator is applied to the frequency- controlling diode, to change its capacitance and to restore the oscillator frequency to its assigned channel. The transmitter is relatively simple because of the constant power require- ments of an FM signal. Circuit bandwidths can be adjusted by variation of circuit Q to obtain sufficient bandwidth for transmission of the important side frequencies. The FM receiver of Fig. 15.9 follows the general design of the super- heterodyne up to the detector. At that point a limiter-discriminator circuit is inserted to change the frequency variations to amplitude variations. The audio amplifier following the discriminator is standard. To provide for adequately large frequency deviations to reduce inter- ference, FM signals are used in the frequency bands above about 40 MHz. An I.F. of 10.7 MHz has become standard so that image interference will not be serious. The l.F. of 10.7 MHz also permits the design of double-tuned transformers with adequate bandwidth to handle the FM deviations. With 200-kHz radio-frequency bandwidths, some loading of the tuned circuits with parallel resistances may be necessary to obtain the needed bandwidths. I /,. + <V„ A + a/„ R.F. Amplifier Mixer Amplifier Limiler Discriminator ( f. h Oscillator Audio Amplifier -4 Figure 15.9 An FM receiver. 15. 10 A Radar System The radar system of Fig. 15.10 illustrates the manner in which electronic systems are designed by the assembly of relatively simple component circuits and functions into an ultimate complex objective. , A typical radar system employs a pulse sequence as in Fig. 15.11(a), transmitting a short very powerful pulse at a rate of perhaps 400 per second. This radio signal travels to a distant target and a very small portion of the energy is reflected back to the receiver. The time taken for the round trip is 369 370 Radio Systems Antenna Rotation 2.5 ms- CRO Screen <"> (b) Figure 15.11 (a) Transmitted radar pulses ; (b) received radar signal as presented on the CRO plot. a measure of distance to the target and is plotted as radial distance on a cathode-ray oscilloscope screen with a linear radial sweep, rotating in step with the rotating antenna. The returned pulse is used to brighten the scope display at its instant of arrival, presenting a visual dot at the target position, as in Fig. 15.11(b). The transmitter starts with a pulse generator, at 400 Hz, followed by a limiter producing square waves. These are used to produce short pulses at 400 times per second. An oscillator at 30 MHz drives modulator I, which is turned on by the pulses as in Fig. 15.1 1(a), and results in pulses of 30 Mhz signal with pulse lengths of a fraction of a microsecond. By mixing with another oscillator at 270 MHz, the final pulses are obtained at 300 M Hz. These are amplified to hundreds of kilowatts and radiated in a very narrow beam by a sharply directive antenna. While the pulse is transmitted, the receiver input is blocked to avoid overload. The receiver input is opened after the pulse is sent to await the returned signal or echo. The echo pulse will be at 300 MHz ±A, where A represents a shift in frequency if the target is in motion. This is the Doppler effect and A = Ivfjc, where v is the target velocity and c is 300 X 10«, the velocity of radio waves in meters per second. The received echo is amplified at 300 MHz and then mixed with the 270-MHz oscillator frequency in the first translator. The signal is there converted to 30 MHz ± A; here wide-band amplification is used to preserve the pulse waveform. The signal is then mixed with 30 MHz from oscillator I. Retained in the output is the pulse envelope at 400 repetitions per secpnd and this is passed to the cathode-ray oscilloscope to control the brightness of the spot on the screen. The delay gate can be used to open the detector circuit at a given time after the pulse is transmitted so as to receive only a single returned pulse. In Review Questions 371 automobile speed measurement on the highway, this gating allows the observer to concentrate on the speed of only one target. The basic circuit form of the receiver is that of the superheterodyne. To the equipment above must be added numerous power supplies and control equipment for feeding the antenna position into the oscilloscope. While rather easy to describe, a radar is, in fact, a complex system. 15. 1 1 Frequency Classification for Radio Signals Portions of the broad radio spectrum have varying characteristics and in describing radio waves and the equipment suited to them, we have the broad classification of Table 1 5. 1. TABLE ISA Radio-Frequency Classification Hand Classification Frequency Range Use Low frequency (LF) Medium frequency (MF) High frequency (HF) Very-high frequency (VHF) Ultra-high frequency (UHF) Exlremc-high frequency (KHF) 30-300 kHz 300kHz-3MHz 3-30 MHz 30-300 MHz 300 MHz-3 GHz 3-300 GHz Marine point-to-point; navigation systems Commercial broadcast Moderate and long-distance communications Television, FM, aircraft navigation Television, radar Radar, space communica- tions, radio relay REVIEW QUESTIONS 15.1 What is meant by the signal-to-noisc ratio at the receiver input? 15.2 Why do receivers for signals from space use input circuits cooled to liquid- air temperatures? 15.3 How does noise vary with bandwidth received? 15.4 What is meant by the noise figure of a receiver? 15.5 What is thermal noise? 15.6 What is a bit of information? 15.7 In computing information content of a signal, why is the logarithm taken to the base 2? 372 Radio Systems 15.8 You are receiving an important telephone conversation and ask the caller to repeat a word. What have you done to the channel capacity? 15.9 What are the three factors available for trade-off in increasing the bit capacity of a communications channel ? 15.10 Why is it uneconomic to increase power to improve the channel capacity? 15.1 1 What is the cause of heterodyne interference in AM reception ? 15.12 What determines the bandwidth of an AM signal? 15.13 What situation leads to a steady whistle in the output of an AM receiver? 15.14 List the major circuit functions employed in a superheterodyne receiver. 15.15 Name two major advantages of the superheterodyne receiver. 15.16 What is meant by I.F.? 15.17 What is the reason that we can obtain very high signal gain in a superhetero- dyne receiver? 15.18 What is an image frequency? 15.19 A signal at 970 kHz is being received with an oscillator at 1430 kHz in a superheterodyne receiver. What is the I.F.? What will be the frequency that might be received as an image signal? 15.20 Name two advantages in the use of SSB over double-sideband AM. 15.21 Why must the carrier reinsertion oscillator of an SSB superheterodyne receiver be very stable? What are its stability limits in frequency? 15.22 What is a transceiver? 15.23 Can you see an advantage for the transceiver form of SSB transmitter and receiver? 15.24 Name several advantages of FM over AM. 15.25 What is the capture effect in FM reception? 15.26 From the Hartley-Shannon law, explain why increasing the bandwidth improves FM reception. 15.27 What causes the Doppler effect in a received radar signal? 15.28 The time from transmitted pulse to echo reception in a radar set is 30.5 /is. How far away is the target ? 15.29 What frequency range is covered by VHF signals? 15.30 What is a major service employing VHF frequencies? 15.31 What frequency range is covered by UHF frequencies? PROBLEMS 15.1 A teletypewriter uses a code with five possible positions for holes in a paper tape per letter symbol. Letters and spaces are sent at the rate of 360 per minute. What is the information rate in bits per second? Problems 373 15.2 A radio receiver has an input resistance of 70 £2. A signal of 4.7 //V is applied along with a steady noise voltage of 0.97 /zV. What is the signal-to-noise ratio at the input? 15.3 The receiver of Problem 15.2 has a noise figure of 3.7 dB. What is the signal- to-noise ratio in dB at the receiver output? 15.4 How many bits can be transmitted per second through the channel repre- sented in Problem 15.2 with a 3-dB bandwidth of I0 5 Hz? 15.5 The signal received in Problem 15.2 is reduced to 1.7 fiV across the 70-S2 input circuit. With a 3-dB bandwidth of 10 s Hz and circuit temperature of 300°C absolute, what is the signal-lo-noise ratio at the input? 15.6 A wirephoto picture size is 12.5 cm x 18 cm and it is scanned at a rate of 40 lines per centimeter, with an equal resolution or number of dots along the lines. We assume that the eye can see 10 different levels or density gradations in the picture. Determine the SIN ratio in decibels required for the channel, of bandwidth 1200 Hz, if the picture is scanned in 3 minutes. 15.7 A superheterodyne receiver is tuned to a signal at 1.85 MHz. A signal at 2.76 MHz is found to interfere. What is the reason? What is the I.F. of the receiver? What is the receiver oscillator frequency? 15.8 A superheterodyne receiver tuned to a signal at 21.7 MHz has its oscillator at 25.2 MHz. What is the l.F. of the receiver? What is the possible image frequency? 16 Digital Circuits Digital signals, using pulses, have become an increasingly important part of electronics in recent years, with the widening application of data processing and the digital computer. Beneath the complexity of these devices we find relatively simple and inexpensive circuits. This simplicity results from the fact that the circuits employ only two current levels or slates, ON and OFF, in a binary or two-level code. For a transistor to discriminate among 10 levels of current for decimal numbers would place an almost impossible requirement on transistor ac- curacy. But electronic devices are well suited to a binary code of on and off pulse signals, which require only that the transistors operate at saturation (ON) or cutoff (OFF). The signal-present slate is usually designated 1 and the off state as 0; thus binary or two-level numbers are represented by chains of on-ofl" pulses or l's and 0's. There are two basic types of circuits used in handling binary signals. They are logic on-off gates and multivibrator switches. We shall show how these are combined to process digital signals. 16.1 Binary Numbers The decimal number system, with a base or radix of 10, has been a part of our lives since early childhood. With the decimal system we emnloy 10 marks or symbols, which wc designate as 0, 1, 2, 3, .... 9. 374 Binary Numbers 376 If we explore the meaning of position in decimal numbers, wc shall sec that a numbering system with a base other than 10 is quite possible; wc might use 2, 3, 8, or 9 as examples. Each position or place in a decimal number car- ries with it a weighting factor expressed in powers of 10: Power of 10: 10« 105 10* 10 J 10* 10' 10° Decimal point Weight of 1.000,000 100,000 10,000 1000 100 10 1 position: We use a zero to indicate that a particular weighted value is absent; we use our numbers, 1, 2, 3, . . . , 9 to tell us how many of a particular power of 10 are present at a position. For instance, 521 in the decimal system employs the first three positions to the left of the decimal point and may be expressed 521 = (5 X 10 2 ) + (2X 10') + (1 X 10°) = 500 + 20 + 1 The position of a digit is weighted by 10 2 = 100, 10' - 10, 10° = 1, respec- tively. In the binary system of numbers, the idea of position is the same as in the decimal system but powers of 2 are used for the weights with each position. Only two symbols are used, 1 and 0. The weighting factors are Power of 2 2» V 2« 2' 2* 2> 2"- 2' 2° Binary point Weight of 256 128 64 32 16 8 4 2 1 position (decimal value) The decimal number 325 is expressed as 101000101 in the binary system. This means (1 x 2») -(Ox V) + (1 x 2») + (0 x 2 s ) + (0 X 2*) + (0 x 2 J ) + (1 x 2 2 ) + (0 x 2') I- (1 x 2°) In decimal values we have 256 + 64 + 4 + I, which totals 325. The pre- viously used decimal 521 would be written 1000001001. In the decimal system, a decimal fraction such as 0.812 is expressed as 0.812 = (8 x 10"') -f (I x 10" 2 ) + (2 x 10" 3 ) Similarly the binary fraction 0.1 101 means 0.1 101 = (I x 2-") + (1 X 2" 2 ) |- (0 X 2" 3 ) + (1 X 2-) 376 Digital Circuits Giving this the weight in decimal numbers = 0.500 + 0.250 + 0.062 = 0.812 (decimal) A simple method for conversion of a decimal number to binary represen- tation employs repeated division of the number by 2. The remainder of I or after each division becomes a digit of the binary number. For the decimal number 232 we have Least significant digit Remainder 232 H- 2 = 116 116 -r 2= 58 58 ■¥ 2 = 29 29 + 2 = 14 1 14 -f 2 = 7 7 -:- 2 = 3 1 3 -r 2= 1 1 1-4-2= 1 Most significant digit The last 1 obtained is the largest digit in the binary number. For decimal 232 we have 1 1 101000 as the binary expression. Fractional decimal numbers may be converted to binary form by succes- sive multiplications by 2. For each step that results in a 1 to the left of the decimal point, record a binary 1 and carry on with the fractional portion of the decimal number. With a to the left of the decimal point, record a binary and carry on. For instance, to convert decimal 0.9375 to binary form, we operate as follows: Binary 0.9375 x 2 = 1.8750 1 0.8750 x 2 = 1.7500 1 0.7500 x 2 = 1.5000 1 0.5000 X 2 = 1.0000 1 0.0000 x 2 = 0.0000 Most significant digit Least significant digit The binary equivalent of decimal 0.9375 is expressed as 0.1 1 1 10. The largest digit is the first binary number obtained and it is placed to the right of the binary point. The requirement for only two symbols in binary simplifies our electronic circuits but we offset this simplicity with the necessity for handling many more digits in the binary representation. For instance, decimal 10 is 1010 in binary. A digit in binary is referred to as a bit, from the initial and final letters of binary digit. Binary Arithmetic 377 16.2 Binary Arithmetic Addition and subtraction in binary numbers is easier than the procedures used in the decimal system. Four rules apply for addition and these can be stated: + 0-0 0+1-1 1+0=1 1 + 1=0 with a forward carry of I A carry is handled similarly to decimal system procedure. Binary addition can be demonstrated in the following: Binary Decimal 1 101 1 27 1011 11 10000 Sum 1 11 Carry 00110 Sum I Carry 100110 38 Subtraction in digital computers is almost universally handled by chang- ing the negative number to its complement and adding. Negative numbers are usually manipulated in complement form. With decimal numbers we form the 9's complement by subtracting each digit of the negative number from 9. We then add 1 to form the 10's com- plement. Suppose we wish to subtract 548 from 2012. The 9's complement of 548 is 451 and 451 + 1 = 452, which is the 10's complement of 548. To subtract, we add the 10's complement and drop 1 from the leftmost digit: Negative Numbers Complementary Subtraction 2012 - 548 1464 2012 + 452 2464 -I 1464 In binary numbers we employ a similar process. To form a l's comple- ment, we subtract each digit of the binary number from I. For instance, the 378 Digital Circuits l's complement of 1001 1 is 01 100; to change this to the 2's complement, we add I so that 01 101 is the 2's complement. To subtract 1001 1 from 1 1001, as an example, we add the 2's complement: 2's complement 11001 01101 100110 1 00110 after subtracting 1 from the leftmost digit. Since 1 1001 — decimal 25 and 1001 1 - decimal 19, the result should be 25 - 19 = 6; in binary, 001 10 = decimal 6. In the decimal multiplication process, we add the multiplicand to itself the number of times specified by the least significant term in the multiplier, shifting one place to the left and repeating for each term of the multiplier. Binary multiplication follows the same procedure but is simplified because each term needs to be set down only once to represent multiplication by binary I. Thus 10101 x 1011 (decimal 21 x II) leads to 10101 101 1 10101 10101 00000 10101 11 1001 1 1 Multiply by I Shift, multiply by I Shift, multiply by Shift, multiply by 1 Sum — decimal 231 Binary division is carried out by successive subtractions or additions us- ing the 2's complement in each case plus shifts to the right. Thus, with the use of complements, all four of our arithmetic operations are reduced to the process of addition, plus right or left shifts. This greatly simplifies the arithmetic unit of a computer. 16.3 Binary Codes To convert from the decimal system of the business community to the binary system in the digital computer has called for the development of computer codes. Foremost among these is the binary-coded-decimal (BCD) representa- tion. The BCD code uses four binary bits to represent each of the 10 decimal digits. This form is also called the 842 1 code, a name derived from the weight of each the four binary digits. The code groups are simply derived from binary representations as shown in Table 16.1. Other Number Systems 379 TABLE 16.1 The BCD Code Decimal Binary Decimal Binary 0000 5 0101 1 0001 6 0110 2 0010 7 01 1 1 3 0011 8 1000 4 0100 9 1001 The decimal number 3582 would be represented in four code groups as 0011 0101 1000 0010 Binary-coded-decimal form is frequently used at computer input and output. Switching circuits are available to convert such groups of bits to full binary number representation or to decode BCD groups into decimal numbers. Such circuits are usual at the output of most digital-reading instruments, such as digital voltmeters. The number of bits employed in a code increases as does the number of symbols represented; that is, three bits are sufficient to transmit the eight decimal numbers 0, . . . , 7, while four bits are needed to transmit decimal numbers 0, . . . , 15. To transmit the English alphabet of 26 letters requires that 2" > 26 bits be used; with V = 32, a five-bit code allows 32 difierent characters to be represented and the letters, punctuation marks, and start- stop signals can be transmitted. This is the alphanumeric code used for teletypewriters. AC /-mi There is also in common use a code with seven bits, known as ASCII (American Standard Code for Information Interchange). With V =-■ 128 com- binations of bits, the numerals, capital letters, and lowercase letters are available. Actually there are 64 characters and 64 operational controls. An example of the latter is the group 0001 010, which calls for a line feed or the movement of the printing position to the next line. The computer can readily differentiate between a control function with the first two bits as zeros and an alphanumeric character when the first two bits are not both zeros. Binary digits are sometimes handled in groups called bytes. The number of bits in a byte is not standardized but in one system a byte consists of eight binary bits, which might include two decimal digits in BCD code or one alphanumeric character in an eight-bit code. 16.4 Other Number Systems Another number system employed in computers uses the base 8 and is called the octal system . By processing base-8 numbers in the binary-coded form, we need employ only the 1,0 representation or the on-ofl" switching of binary 380 Digital Circuits numbers. Therefore we can use ihe base of 8 without requiring our electronic devices to recognize more than the usual on-off states. The number positions are given weights of powers of 8 and the symbols employed are 0, 1, 2, . . . , 7. The number 352 in octal means octal 352 = (3 x 8 2 ) |- (5 x 8') + (2 x 8°) = (3 x 64) 4- (5 X 8) +(2 X I) = 192 + 40 + 2 = 234 decimal To transmit octal 352 in binary-code groups we use 0011 0101 0010 Since 7 is the largest number to be represented in octal, we could reduce this to 011 101 010 Note that the binary system representation for decimal 234 is OTTTOTOTO so that if a binary number is segmented into groups of three bits, we have the binary code for octal numbers. This easy conversion from binary numbers to TABLE 16.2 Number Systems Decimal Binary Octal Hexadecimal 1 1 1 1 2 10 2 2 3 11 3 3 4 100 4 4 5 101 5 5 6 no 6 6 7 Ml 7 7 8 1000 10 8 9 1001 II 9 10 1010 12 A 11 1011 13 B 12 1100 14 C 13 1101 15 D 14 1110 16 E 15 mi 17 F 16 10000 20 . ,0 17 10001 21 1 11 18 10010 22 12 19 1001 1 23 13 20 10100 24 14 Series and Parallel Processing of Bits 381 octal binary code is one reason for the employment of octal numbers within a given computer. The representation of decimal 8 and 9 requires four bits in BCD code. Without adding any more equipment, we can expand the BCD representation to a base- 16 system, or a hexadecimal system, with 16 symbols employed as 0, 1,2 9, A, B, C, D, E, and F. Decimal 10 is represented as A. Table 16.2 shows the relationship of the several number systems dis- cussed. Subscripts are used to identify the number system employed. For example, 352 as an octal number would be written as 352„ ; 01 1 in binary representation would be 01 1 2 ; and decimal 654 would appear as 654 l0 . 16.5 Series and Parallel Processing of Bits The internal language of the digital computer is in the form of binary num- bers and codes. The binary signals arc handled as timed chains of pulses. A clock or timer generates the basic frequency, as shown in Fig. 16.1(a), and binary switches operating in on and off states code this waveform to represent binary data in on (1) and off (0) pulses, as shown in Fig. 16.1(b). The pulse chains may actually be positive and zero, zero and negative, or positive and negative in amplitude and there are many codes in which the data may be transmitted such as BCD or the seven-bit ASCII code. There are two basic methods of handling bits in data processing. When transmitted over a wire line or a radio channel, the bits arc sent in series and operated upon in sequence; the pulses in Fig. 16.1(b) may be visualized as sliding off the page to the right, with the first pulse being the most significant bit of the number. In parallel operation, the bits in the figure may be thought of as sliding down the page simultaneously in four separate channels; the weight ascrj^l to each bit is determined by the channel in which the pulse appears. 'Mim? j Most ■*"" Significant Bit Series 1 1 1 ** Output Binary 1 101 111! Parallel Output (a) (b) Figure 16.1 (a) Clock or timing pulses; (b) binary code 1101 = decimal 13. T 382 Digital Circuits For a signal of 40 bits, the time for serial processing is 40 times that for the processing of 1 bit. With parallel operation the 40 bits are simultaneously processed and the time is approximately that for operating on 1 bit. Thus parallel operation would be 40 times as fast but requires 40 times as much equipment. For reasons of speed, most digital computation is done with parallel processing. Registers or storage elements are used to accumulate n bits as they are received in series and the storage is periodically emptied or (lumped into ii parallel channels. 16.6 Logic Operations in Addition It has been demonstrated that the basic arithmetical operation in digital computation is that of addition. To further analyze the addition process, we again carry out an addition with binary numbers A and B: A ion B Oil I [100 11 Sum Carry, C, 1010 Sum 1 Carry, C 2 10010 Sum The requirements for the addition operation are summarized in the table below, in which columns A, B, and C, provide for all possible combinations of or I input signals for these variables. The columns S and C z arc the required results, reasoned from the addition example above and confirmed by the addition rules of Sec. 16.2. A B c, 5 Ci 1 1 1 1 1 1 I 1 ] 1 1 I 1 I 1 1 1 1 • 1 1 The addition will be carried out in parallel channels so that one adding circuit will handle one bit from A and one bit from B. The process is not Logic Switches 383 numerical in nature but requires circuits that provide I- or 0-Icvel output signals in response to several I- or 0-levcl command signals at the inputs. Specifically, digital operations utilize circuits that recognize the presence of a pulse from one circuit and the presence of a pulse from a second circuit, as well as when a pulse from one circuit or a pulse from a second circuit is present. Also there must be recognition of a carry pulse C,, coming from a preceding bit circuit, and provision must be made to transmit a forward carry C 2 to the next most significant bit channel. The table shows that the sum S equals 1 when A = I OR B = I OR C, = I. other variables = or (16.1) a and b and c, = 1 These statements are reasoned from lines 2, 3, 5, and 8 of the table. We also see that there must be a forward carry output C 2 , or C 2 = 1, when A and fl= 1. C, =0 OR /JandC, = 1, B = Q OR (16.2) B AND C, = 1, A -- OR A AND B AND C, = l These statements result from lines 7, 6, 4, and 8 of the table. To carry out the addition operation we need circuits that yield proper I- or 0-level results from or and and combinations of two or three pulse inputs. We shall later find that a not or inverter operation is also needed. An inverter gives a 0-level output for a 1 -level input, or vice versa. Such circuits that recognize the presence of a group of 1- or 0-level signals at the input and give I- or 0-level output dependent on or, and, not com- binations of these input orders are called logic circuits. They act as off-on switches. 16.7 Logic Switches Logic circuits are often called gales because they are open (OFF) or closed (ON) as called for by the specified combinations of pulse inputs. A logic and gate must provide a "logic-!" output only if all inputs are at the I level. The and operation is illustrated in Fig. 16.2(a) as a series connec- tion of switches. Only if all the switches arc closed or at the 1 condition will an output voltage appear at F; that is, we write in logic algebra ABC = F (16.3) 384 Digital Circuits I Ao- Uo- (o- <a) (1)1 Figure 16.2 (a) Switches in an and circuit; (b) and logic-circuit symbol. and read this as A and B and C equals F. The variable F is equal to 1 if the switches arc all closed ; F — if any switch is open. A table of switch outputs for an and circuit with A and B inputs is A B F 1 1 1 1 1 AND A circuit symbol for an and circuit is drawn in Fig. 16.2(b). A logic or gate must provide an output at "logic- 1" level if any one or more of its inputs is at the 1 condition. The or operation is illustrated in Fig. 16.3(a) as a parallel connection of switches. If switches A or B or C, or any combination, is closed, the circuit is complete and F= I; that is, in logic algebra A + B+C=F (16.4) which is read as "A or B or C equals F." A table of switching outputs for an OR circuit is A B F 1 1 1 1 1 1 1 A circuit symbol for an or circuit is shown in Fig. 16.3(b). The concepts of multiplication or addition should not be associated with the indicated symbols in Eq. 16.3 and 16.4; the equations are intended to convey ideas of switch connection. A logic not circuit supplies the inverse of any operation and the inverse of switch A is written A {A not). If A — 1 , then A = 0, and vice versa. A common-emitter connected transistor often supplies the not operation with its inversion of signal. Logic Switches 385 ► /•' Ao- «o- Cc- (a) (b) Figure 16.3 (a) Switches in an or circuit; (b) or logic-circuit symbol. By combining the and and not operations, we can form a nand (negative and) gate. A table of switching operations is A B F 1 1 1 1 1 1 1 NAND A circuit symbol for a nand operation is shown in Fig. 16.4. Similarly, if we combine or and not gates, the result is a nor (negative or) operation. An operations table for the nor gate is A B F 1 1 1 1 1 A circuit symbol for a nor gate is drawn in Fig. 16.4. /lO- fio- Ao- F = AB Bo- F = A+li (a) (b) .-to- (c) Figure 16.4 (a) nand symbol; (b) nor symbol; (c) not, or inversion, symbol. 386 Digital Circuits Note that the results of nand and nor operations are exactly the opposite of and and or, respectively. 16.8 Logic Voltage Levels In order to explain the operation of actual logic-switching circuits, it is necessary to choose voltages to represent logic- 1 and logic-0 conditions in the gate circuits. Usually the choices arc made to give 1. Positive logic, in which we make the 1 -logic level more positive than the 0-logic level. Frequently the assigned voltages are r-5 V for the I level and V or ground for the 0-logic level. 2. Negative logic, in which we make the logic- 1 level more negative than logic 0, and voltages of —5 V and V are often assigned. Our descriptions of gale circuit operation will be based on the selection of positive logic. 16.9 Diode Logic (DL) Gates Many different circuits have been designed to develop the gate functions described in Sec. 16.7. With diodes employed as switches, diode logic (DL) gates will first be discussed because of their simplicity. An and circuit is shown in Fig. 16.5(a); it is drawn with three inputs but the actual number may vary. + 5V=K CC AND fl C Oulpul Output + 5 V + 5 V + 5 V + 5 V + 5 V + 5 V + 5 V +5 V + 5 V + 5 V + 5 V + 5 V + 5 V Ao- tfo- Co- (b) ABC (O Figure 16.5 (a) Diode logic and gate; (b) ouiput table; (c) symbol. Diode Logic Gates 387 With positive logic voltage of I 5 V for the 1-logic level and ground for level, the diodes are connected so that 1. Ifo// the inputs arc at logic 1 (4-5 V), the diodes have no voltage across them and are open ; the output voltage goes to I 5 V through ihe load resistor R. 2. If any diode input is at logic (0 V), its diode is forward-biased by V cc and clamps the output voltage to zero or ground. This represents a logic-0 output. These are the actions of an and circuit, as predicted by the table in Fig. 16.5(b). The symbol for an and circuit, is presented in Fig. 16.5(c). Since the output voltage goes to -f 5 V through R and the diodes are then open, the output impedance is R at logic- 1 output. For logic-0 output, the output impedance is that of the sources supplying the conducting diode or diodes. The capacitance of the circuit load must be charged through these resistances and the rise time due to R will usually be longer than the time of fall of the output signal, when the discharge is through the low diode resis- tance. A diode logic or circuit is diagrammed in Fig. 16.6(a). For a positive logic signal the circuit will act so that 1. if any diode input is at logic 1 ( I 5 V), that diode will be conducting and will place —5 V (logic 1) on the output. Two or more I 5-V inputs will produce the same effect as for one : 5-V input. .•1 o- OR «o M- C o- X Output (a) /; + S V + 5 V + 5 V + 5 V + 5V + 5 V + 5 V + 5 V + 5 V + 5 V + 5 V + 5 V (b) Output + 5 V + 5V + 5 V + 5 V + 5V + 5 V + 5 V A o- I) o- C o- A +B + C (c) Figure 16.6 (a) Diode logic or gate; (b) output tabic; (c) symbol. 388 Digital Circuits 2. If all the inputs are at V or ground (level 0), all diodes are open and the output is connected to ground through R and the output is at logic 0. These are the actions of an or circuit, as shown by the table in Fig. 16.6(b). The circuit symbol for an or circuit is drawn in Fig. 16.6(c). In computing systems a circuit may be supplied by many inputs and must absorb the input currents. The number of inputs of similar circuits that can be connected without disturbance of the voltage levels is called the fan-in property of the circuit. The ability of a logic circuit to supply output current for driving other similar gates is indicated by the fan-out property or rating. A fan-out rating of 8 would indicate that a logic circuit could provide the current to drive eight circuits with similar input-current requirements. Due to the variable diode voltage drops, it is not possible to maintain the value of |5 V for the logic-1 level and this variability is a disadvantage of diode logic circuits. This variation is especially serious when many diode gates are used in series since the voltage losses become cumulative. The differ- ence between the 1 and levels may become insufficient for accurate operation of the circuits. Section 16.10 supplies a remedy for this situation. Reasoning as applied above will show that if negative logic signals are employed with these and and or circuits, the operating functions reverse; that is, a positive logic or circuit becomes a negative logic and circuit and a positive logic and circuit becomes a negative logic or circuit. Because of the ready availability of more satisfactory logic circuits, diode logic is now rarely employed. 16. 10 The NOT or Inversion Operation The not function of inversion can be performed by a transistor in the C-E circuit in Fig. 16.7(a). The transistor is driven from saturation for an output at level to cutoff for an output at the logic-1 level, as shown by the output characteristic in Fig. 16.7(b). To ensure saturation, the base current should exceed the amount required at the intersection of the load line and the saturation line in Fig. 16.8; that is, the base current for saturation should be 'rial i I„> The collector current at saturation will be (16.5) /r,..„ = '-££- V rr - V r R Vcc R since V CEi „„ < V cc . Then, to ensure saturation, we should have I B > h FE R (16.6) Integrated Logic Circuits f«-=+5V Oulpui V„ Output Vn < saI > - Logic I Output ■ Logic (») I Logic Input (b) Figure 16.7 (a) Transistor inverter; (b) input-output curve. Figure 16.8 Saturation and cutoff levels. This will ensure a Iogic-0 output for a logic-1 input, as desired for the opera- tion of inversion. The output will swing from V C ei,,u = V for logic-0 output to V cc for logic-1 output. 16.11 Integrated Logic Circuits Manufacturers produce many integrated circuit forms of the basic logic gates for and, or, not, nand, and nor operations. All will perform their stated functions and selection of a particular type depends on the applica- 390 Digital Circuits lion, with choice based upon the relative importance assigned to 1. Speed of switching, usually stated in nanoseconds. 2. Fan-in and fan-out characteristics. 3. Power requirements and rated dissipation; usually in milliwatts. 4. Cost, which usually increases with speed of operation. Each circuit is designed to perform one of the listed basic logic functions and an overall system represents the interconnection of many of the elemental circuits. Frequently four or six similar and independent circuits arc placed on one silicon chip and sold as quad or hex combinations to save space in the logic-circuit assembly. . " In general a manufacturer makes available a complete family or circuits, with compatible input and output voltage levels. The individual circuit forms arc simple, as will be shown. The internal circuit designs of typical units will be discussed here only to indicate the reasons for performance differences of the circuit types. 16.12 Diode-Transistor Logic (DTL) In order to improve the fan-out capabilities of diode logic circuits and to maintain a standard logic- 1 level at the output, a transistor amplifier may be added to the output of the diode logic circuits and this leads to a circuit family known as diode-transistor logic (DTL). When the transistor is connected as an emitter follower, the output cur- rent is increased without loading the diodes. The transistor is more usually connected in the C-E circuit, however, and it then performs the not function. Since an and circuit followed by an inverter performs the nand operation Va Output Output (b) figure 16.9 (a) Diodc-lransistor nand circuit; (b) nor circuit. Diode-Transistor Logic 391 and an or circuit followed by an inverter yields a nor function, nand and nor circuits are available as illustrated in Fig. 16.9. These circuits with transis- tors are much less sensitive to output loading changes and have higher fan- out ratings than the diode logic circuits. Normal logic-level voltages are also restored at each gate. Resistors /?„ R 2 , and R } adjust the potentials between +K cc and -K cc so that in Fig. 16.9(a), when point * is at ground, the base of the transistor is placed well hclow cutolT and the circuit is immune to random noise pulses. With X at ground, current / is Vcc 1 = rt 2 -i- Ri and Vbb = RJ - y cc Rx + Ri (16.7) 'cc Thus when X is at ground, the base of the transistor is negative and the npn transistor is cut off. The output rises to +V CC or the logic- 1 level. When all inputs are at the 1 level, X is positive and the base of the transistor is driven to saturation. The output goes to V = 0.1 V, which is the logic-0 level, and the circuit is of NAND form. Another integrated circuit for DTL nand operation is shown in Fig. IfclU. Transistor 0. is driven by the diode output and supplies the saturation bias Figure 16.10 A DTL nand integrated circuit. r 392 Digital Circuits current for Q 2 ; g, is not driven to saturation. The speed is reasonably fast and the fan-out characteristics are good. A general disadvantage of DTL circuits is the necessity for two power supplies. 16.13 Resistance-Transistor Logic (RTL) The resistance-transistor logic circuit family replaces the individual diodes of the DTL circuits with the base-emitter junctions of transistors; a nor circuit form is shown in Fig. 16. 1 1 as an example. The use of transistors instead of diodes does not increase the circuit complexity or cost when integrated circuit production methods are used. r cc :r, *3 i — vww -M- €> R 2 I — WW- Qi K 2 i *Wvv- Output = A +fl + C Figure 16.11 RTL-nor circuit. Introduction of a sufficiently positive pulse (logic 1) to any input will drive the transistor to saturation. If two or more of the inputs are driven at the same time, the output voltage across the parallel transistors remains at the saturation level. The operation is that of or and this is inverted in the respective transistors. The result is that of a nor circuit, with logic-0 output for any logic- 1 input to A or B or C. Resistors R 2 are present to prevent the emitter-base junctions from short- circuiting the pulse sources. The input capacitance of the transistor must be charged through resistor R 2 and this introduces a delay. To allow fast pulses to charge the internal capacitance more rapidly, speedup capacitance C, is added to bypass R 2 for each transistor. Because of the time needed to dis- charge the transistor capacitances after saturation, however, the circuit is somewhat slower in operation than is the DTL form. The necessity for any one transistor to be able to lower the output from V cc to V CEI , U) means that Transistor-Transistor Logic 393 V cc must be small and the discrimination between logic- 1 and logic-0 levels at the output is limited. 16. 14 Transistor-Transistor Logic (TTL) The transistor-transistor logic circuit family is illustrated by a TTL nand gate in Fig. 16. 12, adapted to integrated circuit manufacture. This circuit can be likened to the DTL circuit, except that the switching diodes of the DTL form arc replaced by separate emitters on the base electrode of a common transistor. If all the input emitters are given a logic- 1 pulse, Q t will be turned off and the input to Q 2 will rise, driving Q 2 into saturation with an output at V ceiuVI or the logic level of 0. Speed of switching is increased by use of the common-base form of circuit, increasing the high-frequency capabilities of the input transistor. The base of Q 2 is supplied through the low-resistance collector circuit of Q, and the stored charge in the input of Q 2 can be rapidly removed upon switching. The TTL family of circuits operates with switching speeds of 10 to 20 ns (nano- seconds); operating clock frequencies can be as high as 30 MHz. The gate output is either at logic 1, with Q, in saturation and Q, cut off, or at logic 0, with Q t cut off and Q y in saturation. Because of the manner in which the output circuit is usually drawn, it has been given the name of "totem pole" circuit. It is assumed that when Q 3 turns on, Q t turns off simul- taneously, and vice versa. Both transistors are on for part of the transition, however, and the output circuit then shunts current to ground. This current is limited by the low value of R. The result is that the circuit draws a spike of + 5 V<?f tr F=ABC Figure 16.12 77X-NANr> circuit. 394 Digital Circuits current (a glitch) in each transition and this abrupt current drain may cause a spiked voltage drop on the V cc line, which is transmitted as electrical noise to other circuits supplied by that line. These noise pulses can cause random switching of circuits in which the voltage difference between logic 1 and logic is not great. If many gates switch simultaneously, a large peak current may be required from the power supply. In addition, the transition pulse of current represents power consumption and the power taken by TTL circuits increases with circuit operating rate, or the rate of the system clock. Under quiescent conditions the power may be only 6 mW per gate but at a clock rate of 20 MHz the power consumption may increase to 20 mW per gate. A great variety of related and compatible circuit functions is available for TTL system design. 16.15 Emitter-Coupled Logic (ECL) Circuits When a transistor is in the saturation state, it has a base current higher than necessary and excess charge is stored in the base region and in the collector- base junction region. A transistor cannot change to the cutoff state until this charge is removed and the charge transfer slows transistor switching. Emitter- coupled logic (ECL) circuits obtain greater speed of switching by operation of the transistors in a nonsaturated condition, through limiting the lowest col- lector voltages to values above V CBUu) . An ECL circuit for the or, nor function is shown as an example in Fig. 16. 1 3. Figure 16.13 ECL-OR, NOR gate. CMOS Logic Circuits 395 With fixed bias, transistor Q t supplies a constant current to the emitter resistor R E ; this current is less than the saturation collector current. A logic- 1 input voltage to Q, will turn on that transistor and drop the output voltage at Z. As the switch transistor Q, increases its current, the increased bias across R E causes the current in Q 4 to fall and the drop across R E is maintained constant, but with current from Q, replacing the current from Q t . Reduced current in Q A raises the output voltage at Z and with outputs at Z and Z the circuit provides its own inverted output. The circuit is very fast, operating to switching speeds of 70 MHz; gives simultaneous or and nor outputs; and has high fan-in and fan-out capability. A complete logic family is available. 16.16 CMOS Logic Circuits Because of major differences in the design and operation, the complementary- metal-oxide-semiconductor (CMOS) series of logic gates will be given more extensive treatment. + K DD l\ S \U D D Q 2 Off j D <?i s V Dn = S V Q. On / Q. Off I Q 2 On \ \ \ \ X (a) 2 (b) Figure 16.14 (a) Basic CMOS inverter; (b) transfer characteristic. The CMOS switch employs FET enhancement-mode transistors in both /j-channel and w-channel forms, justifying the complementary name. The basic switch appears as an inverter in Fig. 16.14(a). This circuit shows/?- and /(-channel units connected in series across a power supply and with a com- mon gate input. These devices are diffused on a monolithic silicon chip, by processes that will be described in Sec. 16.18. In the ^-channel transistor Q 2 , the majority carriers are electrons. A posi- tive gate-to-source voltage greater than a threshold value V T will increase the channel current. For a gate voltage at ground or source potential, the channel is cut off. 396 Digital Circuits For the /^-channel unit Q„ the majority carriers are holes. A gate voltage negative to the source S increases the channel current; for the gate at source potential the channel is cut off. With the gates connected together, a positive input V„ equal to V Du , will turn on the //-channel Q 1 and turn off the /j-channel unit Q,. With the gates at ground, the //-channel gate is at source potential and less than V T ; Q 2 is cutoff; the gate of Q, is then negative to its source Sand <2, conducts heavily. The effect of a common input voltage to both gates is complementary and results in a push-pull action of the two transistor elements. Figure 16.14(b) shows the input-output transfer curve when the power supply is V DD = -f 5 V. When V, is near +5 V, the gate of Q 2 is at • 5 V to its source at ground and Q z is on. The gate-to-source voltage of Q, is then zero and less than the threshold voltage, however, so that Q, is in an off con- dition. The device is therefore operating in the right half of the transfer diagram; it appears to have a resistance of a few hundred ohms through Q 2 to ground. The resistance of the off transistor will be in excess of 1000 MQ. The current through both devices in series will be less than 5 nA, resulting in very low power dissipation. We now place the gates near V or ground. The conduction conditions reverse, g 2 is off and Q, is on, and the output voltage reaches — V DD — • 5 V. Operation is in the left half of the transfer diagram. The quiescent current through both devices is again of 5-nA order. During the switching transition a small current passes as shown by the dashed curve on the transfer charac- teristic. With positive logic- 1 input, the output voltage is at V and in the logic-0 condition; with Iogic-0 input, the output is at —5 V and in the logic-l con- dition. The device is therefore an inverter or not logic circuit. The switching time will approximate 25 to 200 nS. Because the circuit switches near one-half of V DD , its immunity to random circuit noise is good. Because of the very thin oxide layer that serves as gate insulation, the diode D is shunted between gate and ground to reduce negative overvoltages that might break down the oxide insulation. 16.17 NAND and NOR Circuits with CMOS Logic By adding devices in parallel or series, the nor and nand circuits in Fig. 1 6. 1 5 can be obtained with CMOS logic. In Fig. 16.15(a), if we make either input A or B positive, we turn on Q, or Q t ; but making A or B positive alS*o turns off either Q, or Q 2 and thus we have V„ = 0, or logic 0. We find the same result for both A and B positive. If we place A and B at ground potential or logic 0, transistors Q x and Qi NAND and NOR Circuits with CMOS Logic 397 + 5 V (a) (b) Figure 16.15 Positive logic CMOS: (a) nor gate; (b) nand gale. are turned on and Q t and Q t are turned off; this is the condition for V = -f5 V, or logic-l level. The operation table is A B Vo 1 1 1 1 1 and we can identify this circuit as giving a nor output. The circuit in Fig. 16.15(b) is an upside down version of that in Fig. 16.15(a). If A and B are positive or at logic 1, Q 3 and Q t arc turned on and V„ = 0, or logic 0. If cither A or B, or both, arc at ground or logic 0, then Q, or Q 2 arc on but Q 3 or Q 4 will be off and so the output becomes V = 1 5 V, which is logic I. The operation table is A B v 1 I 1 1 1 1 1 ajxl the circuit is identified as giving nand performance. 398 Digital Circuits By adding an inverter at the output of either circuit we can develop or and and logic circuits. Additional inputs can be obtained by placing more transistors in series and parallel; the input capacitance increases and reduces switching speed. The power requirements are very low, being in the range of 20 /zW per gate for 15-V operation down to less than 1 /*W for 5-V operation. 16.18 CMOS Manufacture The construction of a monolithic CMOS integrated circuit is illustrated by the cross section in Fig. 16.16(b). Manufacture starts with an n-silicon sub- strate wafer having a thickness of about 0.006 in. (0.015 mm). A silicon diox- ide layer is grown over the substrate by heating the silicon and a hole for the deep p diffusion at the left is etched through the oxide. Acceptor impurities are diffused into this large/? region to the desired depth. The original oxide layer is removed and a new layer grown overall. Holes arc etched open for the heavily doped p ■ diffusions at the right; these become the drain and source diffusions for the p-channel device. After the p~ regions are in place, the remaining oxide is removed and a new SiO : layer grown; holes are etched open for the heavily doped n !■ diffusions at the left. These areas serve as the drain and source electrodes for the /j-channel device. Oxide is again removed, regrown, and holes etched for the gate areas. A very thin oxide layer, about 10"" 4 mm thick, is grown over the gate regions and etched away from the metal contact areas elsewhere. Metalization is then added over the gate dielectric areas and for connection to the elements as shown. L nix D (a) n Channel — f" n Substrate T""'' ( ll '"" 1L ' 1 Figure 16.16 Circuit and monolithic construction of the CMOS inverter. The Adder Circuit as a Logic System 16.19 The Adder Circuit as a Logic System To show how these logic circuit elements are connected to produce a com 1 puter subsystem, let us return to the addition process, analyzed in Sec. 16.6. If we identify logic-0 values by the complementary symbol X {X not), we can expand the logic statements of Eq. 16.1, showing that S = 1 when A and B and C, = 1 OR A AND B AND C, = 1 OR /and Band C, = 1 OR A and B and C, = 1 These statements can be made operative by use of inverters to obtain the complementary values, followed by four and circuits of three inputs each, connected to a four-input or circuit. The complete logic system for this portion of the addition operation is shown in the left portion of Fig. 16.17 and yields the sum bit 5. Figure 16.17 Logical adder for one bit. 400 Digital Circuits The second statement in Eq. 16.2, for the forward carry C, = I, results in an expansion as A AND B AND C, = 1 OR A AND B AND C, = 1 OR A AND B AND C, = 1 OR A AND B AND C, = 1 These logic statements can be realized by three more and circuits feeding into a four-input or circuit. Since the last logic statement is identical to the last statement of the first set, the output of that and circuit is used and one and circuit is saved. The result appears in the right portion of Fig. 16.17 and the circuit yields the carry bit C 2 . The complete circuit must be duplicated for each bit of the parallel- processed binary number, with appropriate interconnections for the carry bits C, and C 2 . Such complete adders are available on single integrated chips. 16.20 Multivibrators The name multivibrator designates a group of circuits widely applied for switching as shift registers or temporary memories and as square-wave timing oscillators or clocks. The circuits are basically closed-loop feedback circuits operating with positive feedback. Because of the cumulative effects produced by this feedback, the circuits drive themselves to either of two limit or latch- up conditions, in which the transistors are at either cutoff or saturation. There are two output terminals A and B and when in a latched condition these terminals have potentials that are logic oppositcs as A = logic 1, B = logic 0, for example. Switching can be made to occur between the two latched limits and the logic levels interchange so that A «= logic 0, B = logic I . Three general types of multivibrator are 1. The bistable or flip-flop, which can be triggered from one stable latched condition to the other by an external signal. 2. The monostablc multivibrator, which can be switched from one stable state to the other; it then returns to the first latch-up condition after a time delay. 3. The astablc or free-running multivibrator, which continuously switches between its two limits without application of an external signal; it is a square- wave oscillator. » The Bistable Multivibrator or Flip-Flop 401 The flip-flop is of great importance in digital operations; the monostablc is useful as a delay and timing circuit; and the free-running type is used for the timing oscillator or clock of a computer system, as well as a frequency source. 16.21 The Bistable Multivibrator or Flip-Flop The circuit in Fig. 16.18(a) illustrates the operating principle of the important bistable multivibrator or flip-flop. The circuit employs two inverter amplifiers in a positive feedback loop, with the output of inverter 1 fed to the input of inverter 2 and the output of inverter 2 returned to augment the input of inverter 1. The two stable or latched conditions occur with inverter 1 in saturation and inverter 2 in cutoff and the reverse with inverter 2 in saturation and inverter I at cutoff. The outputs are complementary and if point A is high at logic 1, then B is low at logic-level 0. If an external triggering signal is applied, the circuit may be made to switch and latch in its reverse state with A at low potential and logic-level and B high at logic-level 1. For further understanding, a form of discrete circuit is drawn in Fig. 16.18(b). Assume the circuit is in a latched state with Q l at cutoff and Q z in saturation. The voltage at A is equal to V cc , while that at B approximates zero. Cross coupling from the low voltage at B through R z and R, and aided B s (a) <b) Figure 16.18 (a) Bistable inverter loop; (b) circuit of bistable multivibrator. 402 Digital Circuits by the bias — V cc maintains the base of Q x at cutoff voltage. Cross coupling from A through R, and R, places a positive potential on the base of Q 2 . Thus Q, is held at cutoff and Q 2 in saturation and the circuit is actually in a stable or latched state. A negative trigger pulse may then be applied to R, the reset terminal, and to the base of Q 2 , driving that transistor toward cutoff. The voltage at B rises as the Q 2 collector current drops and by coupling through R 2 the poten- tial rise at B is transmitted to the base of Q„ turning that transistor on. The rise in its collector current then reduces the voltage at A ; this fall of voltage is transmitted through R, to the base of Q 2 and drives that transistor further toward cutoff. This action raises the voltage at B further and the cumulative action proceeds around the loop until the second latched state is reached, with Q, in saturation and Q 2 at cutoff. The voltage at A is then near zero or at logic and the voltage at B is V cc and at logic 1. A negative pulse applied to S, the set terminal, will cause the circuit to return to its original state, with A at logic I and B at logic 0. The time required to transfer conduction from one state to the other is known as the switching time. Fast switching is possible if the transistors are chosen with high values of/V, indicating low values of input capacitance. The time constants associated with the speedup capacitors C should be small with respect to the time between switching pulses to allow the speedup capacitors to recharge. 16.22 The RS Flip-Flop Figure 16.18(b) shows the R and S trigger terminals of a reset-set flip-flop. In Fig. 16.19(a) we have a circuit composed of a cross-coupled pair of nand gates for the multivibrator switch, with input logic supplied by two additional nand gates. This circuit will act as does an RS flip-flop, although the actual circuit may be much more complex. s Q r IT R Q (a) » (b) Figure 16.19 (a)NAND gale simulation of an RS flip-flop; (b)/?S flip-flop symbol. The T or Toggling Flip-Flop 403 The circuit will trigger on the positive-going edge of the clock pulse in- serted at Cif a positive I exists at the S or R inputs. A logic- 1 input to 5 with the input to R at will cause Q to go to I and Q to 0; this is the set state. If R is given a logic- 1 signal when S is at 0, the output condition becomes Q = and (2=1; this is known as the reset state. Simultaneous inputs to S and R will not give outputs from the nand logic circuits when a clock pulse arrives and the flip-flop is left in its previous condition. Simultaneous 1 inputs to R and S will cause circuit confusion, however, since the circuit will attempt to reach logic on both outputs. This is an input condition that must be avoided. The circuit operations arc predicted by s R Q Q Unchanged 1 1 1 I 1 1 ? ? In effect the RS flip-flop indicates and remembers the last input signal received. The switching action is synchronized with the arrival of a positive- going clock pulse. Input pulses need be only long enough to initiate the switching action programmed by the R or S signal and the input pulse can then be removed. 16.23 The T or Toggling Flip-Flop The T multivibrator in Fig. 16.20 will switch between alternate states on successive negative trigger pulses. The two diodes D x and D 2 arc steering diodes, which direct the trigger pulses to the base of whichever transistor is on. A reset input may also be added to the base of a transistor to set the initial condition of the circuit before toggling starts. With Q, off and Q 2 on, a - 5-V negative trigger pulse is applied and takes point X down to f 5 V. Diode D 2 is reverse-biased between C at -| 5 V and Bat V. Diode D, is found to be forward-biased and transmits the negative trigger pulse past A to the base of Q 2 , turning it oflT. Transistor Q t is turned on in normal fashion. The next negative pulse finds D, reverse-biased due to the change in voltages at A and B and, with D 2 conducting, the trigger pulse is directed to the base of Q, to turn it off. The circuit then toggles or reverses its outputs. Toggle flip-flops are used in counters to accumulate pulse counts. Each toggle circuit is known as a scale-of-two circuit since Q 2 switches on once for 404 Digital Circuits Trigger o!' rr = + 10 V (b) la) Figure 16.20 The logglc flip-flop. Iwo input pulses. In switching on, Q z generates a negative-going pulse at B that can be transmitted to a second toggle circuit as a triggering pulse. For two toggle circuits in cascade a pulse is obtained from the last circuit for every 2 2 = 4 input pulses. This is the action of a scale-of-four circuit, as shown in Input o If- C\ TT .v cc C *2 Y />4 -o Output /) Figure*16.2I Scale-of-four circuit. The JK Flip-Flop 405 Fig. 16.21. The count can be extended by use of additional toggles in cascade, n circuits providing for a count of 2". If positive logic signals are used, then the negative-going input triggers are obtained when the trigger pulse goes from -|-V to V and this is known as trailing-edge triggering. 16.24 The JK Flip-Flop The JK flip-flop is the most complex of these circuits. It is similar to the RS circuit except that its operation is predictable when both trigger inputs arc at the logic- 1 level. In that condition the circuit always changes state and com- plements its previous outputs. A circuit that will provide JK operation is drawn in Fig. 16.22; actual circuits arc more complicated but being available in integrated circuit pack- ages makes this internal complexity of little importance to the user. Since each and gate has one input fed back from an output, one of the and gates has a logic- 1 input in addition to the logic I supplied by the clock at T. We also have the J and K inputs to the respective gates and four possi- bilities exist; these are listed in the operation table: J a: Q Q No change I 1 1 1 i I Toggles Signals may be applied and held at J and K but switching occurs only at the time of the positive-going rise of the clock pulse applied at T. J a 1 FP K Q (a) (b) Figure 16.22 (a) Equivalent circuit for a JK flip-flop; (b) symbol for a JK circuit. 406 Digital Circuits As seen from the table, if both J and K are at logic the and gates arc inoperative and no action occurs when the clock pulse arrives. If both J and K inputs are at logic 1, the action of the clock pulse is as a toggle and the output becomes the complement of the preceding condition. The circuit then operates as a T flip-flop. For./ = 1, K ^- or/ = 0, K = 1, the outputs follow the inputs and the circuit operates as an RS flip-flop. Figure .16.23 illustrates a JK flip-flop as designed with CMOS switches. The transistors designated Q, and Q 2 constitute the basic nor circuit of the RS form of flip-flop, with Q 3 , Q 4 providing the JK features and Q, supplying the clock toggle action. The complexity is not a matter that need concern us when the circuit is designed as an integrated package. 1 DD »h Q <?o- «»Z3\- H fl»» ^ Jo- *r ^ h -oQ -oK -or Figure f 16.23 A CMOS JK flip-flop. The One-Shot or Monostable Multivibrator 407 16.25 The One-Shot or Monostable Multivibrator The basic circuit of the monostable or one-shot multivibrator is derived from the bistable form of circuit by replacement of one of the cross-coupling resistors with a capacitor C. The result is indicated in Fig. 16.24 where we have two inverters in a closed loop, with the positive feedback path between the output of inverter 2 and the input to inverter 1 consisting of the ac path provided by capacitor C. In o. on ^( o Trigger (a) CM Figure 16.24 (a) Cross-coupicd inverters acting as a monostable multivibrator; (b) a monostable circuit. The normal stable condition finds inverter 1 at cutoff. If a positive pulse is given to inverter 1, driving it into saturation, its inverted output will drive inverter 2 to cutoff. The signal is coupled back to the input of 1 and will hold inverter 1 in saturation as long as the charge remains on C. This is a quasi- stable state for the circuit and after the charge drains ofl" C, the circuit switches back to its original stable state in which inverter 1 is cut off. The time duration Tin which the circuit is in the quasi-stable condition is determined by C and its associated resistances and the delay time in that state can be varied by means of a variable resistance. The one-shot circuit is fre- quently used to provide a delayed pulse or to vary the length of a received pulse. It is then known as a "pulse stretcher." A simplified circuit for a monostable multivibrator is drawn in Fig. 16.24(b), with one cross-coupling resistance replaced with capacitor C as the 408 Digital Circuits feedback element. Normally Q 2 is in saturation by reason of the positive bias supplied through R and Q, is cut off because the voltage at fiand the base of Q x is essentially zero. A negative trigger pulse will turn Q 2 to the off condition. As its collector current drops, the voltage at B and the base of £>, rises to V cc , turning Q, on. As the Q, current rises, the voltage at A falls from I V cc to zero and this negative step potential is transmitted through C to the base of Q u placing it in the off condition. This change in base voltage is sketched in Fig. 16.25(b). Transistor Q z is held off until capacitor Ccan recharge and the time delay is indicated as T seconds. When the base voltage of Q z rises to zero, Q 2 turns on and Q, goes to cutoff and the original stable condition is restored. The time of delay is determined from the RC time constant as T^OJRC (s) (16.8) The outputs at A and B are complementary. Trigger Pulse n t = (a) To V. a T Delay II +V tfiBi) 1 (b) <c) Id) Figure 16.25 Circuit waveforms for a monostablc multivibrator. 16.26 The Astable Multivibrator The third version of the multivibrator circuit is the astable or free-running form, which acts as a square-wave oscillator. The circuit is used to provide the square-wave clock signals for digital processing. The astable circuit is derived from the bistable form by replacing both feedback resistors with capacitors, as indicated in Fig. 16.26(a). With feed- back supplied by capacitors, there is no stable state for the circuit and it oscillates with a square-wave output at B and a complemented square-wave output at A, as shown in Fig. 16.27. Vcc .1. :*/. «i r 2 k, : 1 o,-i A' K If II c : \ X •*"c, Q,( JQi j*j ■ ° II (a) (b) Figure 16.26 (a) Astable action by feedback with inverters; (b) stable multivi- brator circuit. + Vcc / = "Bt: + K (a) (b) (O ° r=~0 (d) Figure 16.27 Waveforms of the astable multivibrator. 409 410 Digital Circuits Consider Q t just turned off at / — in Fig. 16.27(a) and (b). The base voltage of Q, will rise from — V^ toward zero as C, charges. When v BB , reaches V, Q, turns on and turns off Q 2 , as shown in Fig. 16.27(c) and (d) at / = r,. The cycle repeats as C 2 charges, after which Q, and Q z again switch, returning to the original condition. The oscillation continues and the frequency is determined by the time constants R X C, and R 2 C 2 . These determine the respective time delays and since these need not be identical, the frequency of the oscillation can be stated as (16.9) / = r, + r, o.7(*,c, -i r 2 c,) (Hz) 75.27 Synchronization of the Free-Running Multivibrator In the freely oscillating form, the rectangular output waves of the multivibra- tor circuit include many harmonic frequencies. This was the reason for the multivibrator name for these circuits; however, the stability of the frequency generated is not great. The circuit can be synchronized lo a standard frequency or pulse chain by applying pulses to the base of the off transistor so that these pulses add to the rising base-voltage wave, as in Fig. 16.28. The added pulses cause triggering of the circuit at a time determined by the pulses rather than by the rising charging curve. The synchronization need not be at the pulse rate but may take the form of frequency division as shown, in which the multivibrator triggers for every n pulses. The figure shows a countdown ratio of 8. The harmonics in the square output waves then provide standard and accurate frequencies covering a wide frequency range. The horizontal- and vertical-sweep oscillators of TV receivers are syn- chronized in this manner to pulses received with the picture signals. I I I I I I I I I I I I I <:.) Vae K V (b) Figure 16.28 (a) Synchronizing pulses; (b) countdown by a factor of 8. The Schmitt Trigger Circuit 411 16.28 The Schmitt Trigger Circuit The Schmitt trigger shown in Fig. 1 6.29 replaces one of the cross-coupled feedback paths of the multivibrator with feedback coupling across a common- emitter resistor R E . The circuit switches at two input voltage levels, one when the input voltage is rising toward the trigger level and the other when the input voltage is falling from above the trigger level. The difference in these levels is called the hysteresis of the circuit. The triggering voltage level is set by V E , the voltage across the emitter resistor R E and due to the current of Q 2 . For input voltages less than V E the input transistor is cut off by this emitter bias, Q 2 being in conduction with a low voltage at B. As v, approaches V E , the collector current of Q, starts to rise, lowering the voltage at A as well as the base voltage of Q 2 . As Q, turns further on, Q 2 cuts off because of the feedback through /?, from A and the voltage at B rises to V cc . A reverse action follows when the input voltage falls from a value above the original V B . The change of output voltage at B versus the input v, is plotted in Fig. 16.29(b) and shows the hysteresis in switching voltage that exists when the input voltage falls from above the V E value. By always approaching the switching level from below V E , the operation will accurately occur at the same input voltage. Thus a switched voltage is available at B when v, = V E , and this voltage change can be used to indicate equality of the voltages for voltage comparison £ Vcc 3 1 \ Q. 1 3 1 o 1 1 1 t 1 1 1 1 Input V, (a) (b) Figure 16.29 (a) The Schmitt trigger; (b) input-output relations. 412 Digital Circuits Decoding Matrices 413 circuits. The circuit also will provide squared output waves for sinusoidal or other pulse forms. In particular, it is used to reshape pulses that have been distorted in transmission, as shown in Fig. 16.30. Input V ; -/A--/A-/A- (a) (b) .2J-L- Figure 16.30 Reshaping of pulses by (he Schmilt trigger. 16.29 The Shift Register One of the most common applications of the flip-flop is in the shift register. This is a form of temporary memory in which data pulses, I and levels, can be transferred serially from one flip-flop to the next flip-flop. Readout of the condition of all flip-flops can be made on call, with the data flowing into parallel channels for further processing in parallel form. In the circuit of Fig. 16.31(a), serial data is continuously supplied from a telephone line or other data channel into the first flip-flop FF,. The input pulse is complemented by an inverter and the pulse and its complement are fed to two and circuits along with the clock pulses. A I input pulse present at the time of the first clock pulse goes into the and circuit along with the clock pulse and the upper and circuit output feeds a logic I to the set input of FF,. If a logic had come from the line, it would have been inverted and sup- plied as a 1 to the lower and circuit along with the clock pulse and a I output would then have gone to the R input, resetting FF, with a at Q. On the next clock pulse the conditions at the outputs, Q and Q, will be transferred through the second set of and circuits to S and R of FF Z ; new data will be supplied to the inputs of FF,. On the third clock pulse the con- dition of FF 2 is transferred to FF t , the state of FF, is transferred to FF ly and the new input pulse enters FF,. The input data pattern flows through the register with identical waveforms, as shown in Fig. 16.31(b). The first stage samples the input data at the instant of the trailing edge of a clock pulse; even though the data input changes state at random times, the data at the output of each flip-flop changes only in synchronism with the clock. If four-bit numbers are used, then gates placed at the outputs 1, 2, 3, and 4 can be activated once every four clock pulses and the bit values of the four- bit number then present in the register will be read into four parallel chan- nels, for translation of serial input data for parallel processing and further Input Datu o Clock Pulse (a) I 2345678° 10 «- JUUUUUUUULJl Input Data Cb) Figure 16.31 (a) A shift register; (b) flow of signals through the register. computation. The addition of more flip-flops to the register would increase the number of bit positions that could be handled from the input data. The shift register can also be used as a delay element. Input pulses may be fed serially to the input of a register of appropriate length and the same data taken out of a later flip-flop, delayed by the time of one clock pulse per stage included in the register. 16.30 Decoding Matrices A decoder matrix is usually a diode logic network, actuated by a shift register as a temporary storage clement, and used to decode binary signals to decimal or other code. The application in Fig. 1 6.32 is intended to translate three-bit BCD numbers into decimal outputs 0, . . . , 7; another flip-flop in the register and more diode logic switches would allow extension to decimal 15. 414 Digital Circuits Decimal Counting 415 + V Binary in Pww no -ww IOI -WW IOO -WW on -ww 010 -WW 001 -WW ooo Shift Register Serial Input Figure 16.32 Decoding matrix of and circuits. The outputs of the flip-flops in the shift register are applied to lines con- necting to diodes, each vertical bus constituting a four-input positive logic and circuit. With -| V connected to the horizontal lines, any diode connected to a Q — flip-flop state will conduct and ground that particular horizontal bus. For any state of the flip-flops, only one bus will not be at zero potential and that bus will place — V at the terminal corresponding to the decimal equivalent of the binary number to be indicated. A similar diode matrix can be designed for any input code by noting that a 1 in the binary number calls for a diode at a Q connection ; a in the binary code requires that a diode be connected at Q. 16.31 Decimal Counting A chain of four flip-flops will count to 2* ■= 1 6 pulses before the last flip-flop returns to its initial state. When using decimal numbers, it is more convenient if we can count by decades and modifications of the basic scaler circuits are available, using feedback, to cause them to count by 10's. Feedback on -» I Change Figure 16.33 A divide-by-10 feedback counter. One such circuit is shown in Fig. 16.33. Initially a reset pulse is applied to place all the flip-flops in the normal condition. Counting is normal up to the eighth pulse, and the conditions of the flip-flops are indicated in Table 16.3. At the eighth pulse, Q of FF, goes from to I and this transition provides a pulse that is fed back to FF Z and FF } to advance them by one pulse each. Including the weight of 2 for FF t and 4 for FF„ the counter is therefore advanced by a total count of 2 + 4 — 6. With the count of 8 already present at the output of FF t and an artificial advance of 6, the count now appears to be 8 + 6 = 14; two more input pulses advance the output to 16, giving a TABLE 16.3 Pulse No. (?. Q\ Qz Qi Qi G, Q* Q* 1 1 1 1 1 1 1 2 1 1 1 3 1 1 1 -4 1 J 1 5 1 1 1 6 1 1 1 7 1 1 1 8 1 1 1 1 8* 1 1 1 1 9 1 1 1 1 10 1 1 1 1 •By feedback. 416 Digital Circuits to l transition at Q of FF t , an output pulse, and resetting all flip-flops to the initial zero count condition. Actually the output pulse is transmitted after N » 2« - 6 = 10 pulses and so we have a divide-by- 10 counter. Additional circuits can be added in cascade for counting of further decades. The condition of the individual flip-flops is indicated in Table 16.3. At the tenth pulse the flip-flop conditions correspond to a zero count and a to I transition pulse is transmitted from Q t . Such decade counters are available as complete integrated circuits. Many variations of the basic scheme are employed as elements in frequency coun- ters. REVIEW QUESTIONS 16.1 Explain the meaning of zero in a decimal number. 16.2 Why is a binary code well adapted for use with transistors? 16.3 What is the weight assigned to each position in the binary number 0101 ? What is the decimal value of that number? 16.4 Convert decimal 812 to its binary equivalent. 16.5 Convert decimal 0.764 to its binary equivalent. 16.6 What is the meaning given to the word bill 16.7 In decimal numbers, what is the 10's complement of 371 ? 16.8 In binary numbers, what is the 2's complement of 1001 10? 16.9 Write the BCD number for decimal 1028. 16.10 What is the decimal equivalent of the BCD number written as 0111 0101 1000 16.11 How many bits arc needed to transmit the decimal number 137 as a binary number? 16.12 What is a byte? 16.13 Write decimal 317 in octal code. 16.14 What is meant by parallel processing of digital signals? 16.15 A signal contains 32 bits per byte. If the time to process one bit is 1.1 /IS, how long does it take to process one byte in series and in parallel operation? 16.16 Describe the operation of a two-input and circuit. 16.17 Describe the operation of a two-input or circuit. 16.18 In logic algebra, what is the meaning of the symbol • ? Of the symbol +? 16.19 What is a nand circuit? A nor circuit? 16.20 Define positive logic; negative logic. Problems 417 16.21 Two voltage levels of -f-5 V and — 5V are available in some equipment. How would you assign these in (a) Positive logic? (b) Negative logic? 16.22 What is meant by the fan-in of a circuit? 16.23 What is the meaning of fan-out? 16.24 What is a logic gate? 16.25 Name one disadvantage of DL circuits. 16.26 What happens to and and or circuits when the logic voltages are reversed? 16.27 What is a not operation? 16.28 Name at least four factors to be considered in the selection of a particular form of logic circuit. 16.29 Name one advantage of DTL over DL. 16.30 Name one advantage of TTL circuits over DTL; also name one disadvantage. 16.31 Name one operating advantage of the ECL form of circuit. 16.32 To what design factor does the ECL family owe its switching speed? 16.33 Describe a CMOS inverter switch. 16.34 Why is the power consumption of a CMOS switch so small? 16.35 What is meant by a flip-flop? 16.36 What is a monostable multivibrator? 16.37 What is an astable multivibrator? 16.38 What is meant by multivibrator-switching lime? 16.39 Why arc speedup capacitors used? 16.40 What are the output conditions represented by a trigger pulse of a flip-flop to the set terminal ? To the reset terminal ? 16.41 Describe the action of an RS flip-flop. 16.42 How docs a JK flip-flop differ from an RS flip-flop? 16.43 What is the function of a T flip-flop? 16.44 What is the cause of the quasi-stable slate in the one-shol multivibrator? 16.45 What is the purpose of synchronizing a free-running multivibrator to a stan- dard-frequency oscillator? 16.46 How would you use a Schmitt trigger? 16.47 What is the purpose of a shift register? PROBLEMS 16.1 Decode the following binary numbers to decimal form: 10110 01010 001 1 1 11010 10101 01011 oino 11000 nioi 418 Digital Circuits Problems 419 16.2 Write the following decimal numbers as binary numbers: 104, 547, 123, 362, 445, 176 16.3 Translate the following decimal numbers to base-8, or octal, numbers: 123, 387, 462, 97 16.4 Translate the following decimal numbers to base-3 numbers: 57, 96, 81, 104 16.5 Perform the following operations in binary arithmetic, with -I meaning addition and x implying multiplication: 110110 I 01 101 1 (a); 1 10010 x 10110 = (c) 101 111 | 100101 - (b); 101010 x 11100 =(</) 16.6 The following numbers are in binary notation: 01011101 01101100 0.1101 10110010 11100011 0.0111 1 101 101 1 10(01 100 0.101 1 (a) Determine the decimal equivalent values. (b) Determine the equivalents in octal notation. 16.7 For the indicated operations in Fig. 16.34(a), write the output expression in words as F A or B D>- (a) (b) /lo- Ho ■£ /lo- C"o- (c) Figure 16.34 16.8 Implement the operations of Fig. 16.34(a) with diode-transistor logic circuits and positive logic, and draw the circuit. 16.9 Derive the operation table for the circuit in Fig. 16.34(a) by writing the table step-by-step. 16.10 Repeat Problem 16.7 for the circuit in Fig. 16.34(b). 16.1 1 Draw the circuit, using DTL gates, to carry out the operation in Fig. 16.34(b). 16.12 For A = 0, B = 1, find the output state F of the circuit in Fig. 16.34(b). 16.13 The waveforms in Fig. 16.35(a) are applied to a nor gate. Draw the output waveform. 16.14 The waveforms in Fig. 16.35(a) arc applied to an and gate. Draw the output waveform. + 6V + 5 •JTTLTL + 5 "2 J r (a) (b) Figure 16.35 16.15 Both inputs to the RTL nor gate in Fig. 16.35(b) are at +6 V. If R, = R z = 10,000 fi, R L -■ 1000 CI. what arc the collector currents of Q, and Q 2 if h fB - 50? Consider the R L drop. 16.16 In the circuit in Fig. 16.35(b), each transistor has a reverse saturation current of 20 fiA in the off state. How many similar inputs could be added before the off-state output voltage drops to 5.5 V? Use the circuit resistances of the previous problem. 16.17 Consider the nor gate in Fig. 16.35(b). How much current can be supplied to a load at »>„ if v„ is not to be less than 5 V for logic I, the gate transistors being in the off state. 16.18 For the RTL nor gate of Problem 16.17, if v, = +5 V, what is the input cur- rent? Will that input current saturate Q, if h rE = 30, V cc = 5 V? 16.19 Write the operation table for the circuit in Fig. 16.34(c). What is the output state when A I, B - 0, C = I ? 16.20 Determine if the two circuits in Fig. 16.36 are equivalent in operation by comparing their operation tables. 420 Digital Circuits Problems 421 /lc flc /Tc flc /lc Be /Tc flc + 4 V (a) (b) Figure 16.36 16.21 Figure 16.37(a) shows a CMOS bistable multivibrator. What are the stable operating conditions for the transistors of this circuit? 16.22 (a) Explain the operation of the circuit in Fig. 16.37(b). (b) What is the purpose of Q x and gj? Note that the circuit does not employ complementary symmetry. 0^ r DD X e 2 K 3 C>3 R (b) Figure 16.37 16.23 Determine the output frequency from an astable multivibrator having timing circuit component values of /?, = 2.7 kQ, C, 1000 pF and R 2 =5.2 kQ, C 2 - 1500 pF. 16.24 The RTL bistable circuit in Fig. 1 6.38(a) is to be changed to monostable form. Draw the circuit and give possible values for R and C to give an off time of 10 /xs for Q 2 . 16.25 Show whether the inverter in Fig. 16.38(b) is driven into saturation If Am = 20, with logic levels of +6 and V applied at A. <-6 v o l'„ (a) (b) Figure 16.38 16.26 If a second trigger pulse is applied to a one-shot multivibrator while it is in the quasi-stable state, what will be the elTect on operation? 16.27 The excess-3 code is sometimes used because no digit is represented by a com- plete null or zero signal : 0011 5 1000 1 0100 6 1001 2 0101 7 1010 3 0110 8 1011 4 01 1 1 9 1100 Design a diode-switching matrix to translate exccss-3 coded numbers to their equivalent decimal values. r 17 Power Control The basic design of a junction transistor is not well suited for switching in high-power applications. For efficiency with high currents, the emitter and collector regions should be of low resistance or of low resistivity material; for high h rB , the base should be very thin. A thin base between a low-resis- tance emitter and collector is not suited to operation at the high voltages needed in industrial switching. By use of four material layers and three junc- tions in series, however, the silicon-control rectifier (SCR) family of devices has been developed to control high currents at high voltages. This family includes various related designs known as the SCR, thyristor, triac, and the gate-controlled switch. 17. 1 The Silicon-Control Rectifier (SCR) In contrast to the continuous control of current in the transistor, the silicon- control rectifier action is that of a trigger able to switch a current on. The current can only be stopped by reducing its magnitude below a certain hold- ing value /„. The four-layer pnpn construction of an SCR is shown in Fig. 17.1(a). We can consider the unit to consist of two transistors in series, as dia- grammed in Fig. 17.1(b). Transistor Q, is composed of layers n t ,p l ,n l and is of npn characteristics and transistor Q, employs layers Pz,n t ,p x and is of pnp characteristics. A gate electrode is connected to/>, . With the gate grounded 422 SCR Characteristics 423 or V a = 0, transistor g, is cut off and its collector current I Cl = I co and consists of the leakage current only. This is the base current to Q z and it is too small to turn that transistor on. The device is open-circuited for V = 0. When we apply a sufficiently large positive voltage to the gate, we turn Q, on. The collector current is l Cl — I Bl and so Q 2 turns on; but the collector current of Q z is I c , — I B , and so Q, turns on further, increasing I Cl = I Bl . The actidn around the Q u Q z loop is cumulative and the device rapidly switches to a conducting condition between anode and cathode. With both bases driven to saturation the forward resistance between anode and cathode is very small. The time required for the cumulative turn-on action is ap- proximately 0.1 to 1 p.s. Except for the initial triggering action, device conduction does not depend on the gate current. Therefore turn-off does not occur when the gate signal is removed since the two base currents are now internally driven. To stop conduction the anode voltage must be removed or the anode driven to a negative potential, reducing the current below /„. Turn-off time is typically 5 to 30 fis. 9+V An Pi "2 Gate P\ "I I Cathode Cathode (a) (b) Figure 17.1 (a) A four-layer switch; (b) two-transistor simulation of four-layer action. 77.2 SCR Characteristics The SCR is normally used with an ac voltage applied and conduction occurs on the half cycle in which the anode is positive. The characteristic for one value of gate current 1 is shown in Fig. 17.2(a), with the circuit symbol of the SCR presented in Fig. 17.2(b). 424 Power Control / C < / - V b - Z 1 / :x^ B f V, + V 1 Zener 1 Region 9 Anode J: Gate < Cathode (a) (b) Figure 17.2 (a) Voitagc-currcnt relation for the SCR; (b) symbol. For a particular value of gate current the SCR will trigger when the volt- age of the wave reaches V B . For larger values of /„ the triggering voltage will be lower. As conduction starts at point B on the voltage-current curve, the SCR voltage abruptly falls to Cand then rises to its peak value along the CD portion of the curve. In the on condition the SCR acts as a forward-biased diode and the curve between C and D is that of a junction diode. A great many combinations of gate voltage and gate current will trigger the SCR but gate voltages greater then 3 V arc usually required. After the peak of the ac current wave is passed on the CD curve, the current value falls along the curve; when it reaches I h , the holding current, the conduction ceases and the current goes to zero. With ac applied, con- duction ceases when the ac sine wave approaches zero. Applications with ac involve the use of a pulse of gate current /„ at the time it is desired that conduction start in the circuit in Fig. 17.3(a). This will beat some angle #, in the wave of ac anode voltage illustrated in Fig. 17.3(b). The average or dc value of the rectified current varies with the triggering angle 6, as shown in Fig. 17.4. For a half-wave-controlled rectifier circuit with a AC J'. Gate v. i SCR o VvW (a) (b) Figure 17.3 (a) SCR control circuit ; (b) rectifier waveform for current control. The Unijunction Transistor 425 resistance load, the output voltage is expressed by fJ = ^ (1 + cos0i) (17 - 1) For the full-wave rectifier circuit the result is twice as great, or £fc = i-(l +COS0J (17.2) Mounting, cooling, and temperature limitations for the SCR follow those previously discussed for the power transistor. Devices available employ gate currents of 50 mA to control operating currents of 50 A or more. ^ E 0.6 s,(b) 0.4 t-\\ *"v 0.2 — id) s "*• . X 20" 40° 60° 80° 100° 120° 140° 160° 180° Figure 17.4 Control of average rectifier current: (a) half wave, resistance load; (b) full wave, resistance load. 17.3 The Unijunction Transistor (UJT) Another trigger device is made with a bar of n silicon having a p junction of aluminum-doped material added below the midpoint as shown in Fig. 17.5(a). With only one junction, the device has become known as a unijunction transistor (UJT). The circuit symbol appears in Fig. 17.5(b). The emitter arrow points in the direction of forward current. The ends of the bar act as base contacts B, and B 2 . Base B 2 is maintained positive at V BB and the bar appears as a resistance of 4000 to 10,000 Q. The current through the bar creates a voltage drop along the bar. At the location of the p emitter the bar is positive to B, and ground by some fraction of V BB , called t\V m . The lowercase Greek letter t] (eta) is called the intrinsic standoff ratio. 426 Power Control °2 T E vVbb 1 *T ~x (a) (b) (c) Figure 17.5 (a) Unijunction transistor construction; (b) circuit symbol; (c) performance curve. If the voltage v EB applied to the emitter is less than t\V BB , then the emitter is negative to the n bar and the junction is reverse-biased. If the voltage v EB is made more positive than i\V BB , the emitter becomes forward-biased and holes move from the p emitter into the n bar and toward fi, . The presence of holes in the bar calls for electrons to enter the region from B x and the increased density of mobile charges lowers the resistivity of the bar between £and B t . The voltage between £and fl, then drops, allowing more holes to enter the bar and results in more electrons entering, rapidly reducing the volt- age v EB from V p to that of a normal forward-biased diode, as illustrated in Fig. 17.5(c). This action can also be explained by use of Fig. 17.5(c) in which the initial current at A is only the reverse value I co . The voltage can rise to the peak voltage V, where v EB = tjV BB = V p , and emitter forward conduction begins. With the entrance of holes into the bar, the bar resistance falls abruptly and the voltage drops to C on the forward-bias diode curve. The valley voltage V. is the lowest voltage value between emitter and base B,. We thus have a device that will rapidly switch from V p to the diode voltage approximating r.. The value of the peak voltage V „ can be predicted for a given V BB by use of V, S nV„ + 0.7 V (17.3) where the term 0.7 V is an approximation to the inherent forward drop of a silicon junction. The device yields an equivalent circuit of the form shown in Fig. 17.6. The diode is that of the junction; the resistances R, and R 2 are those of the ' Triggering the SCR 427 + V m »EB O Figure 17.6 Equivalent circuit for the UJT. two parts of the bar. The value of tj can be found from the resistances of the bar as 1 (17.4) where /?,„ is the value of /?, at l B = 0. The resistance R l0 = 5000 Q and may drop to 50 Q when switched by i E , for a typical UJT. 17.4 Triggering the SCR The circuit in Fig. 17.7(a) will provide a variable-phase voltage for trig- gering an SCR at a desired angle 6, in the ac cycle. Either R or C may be varied to shift the phase of the control voltage V c , derived between points B and £ of the phase shift bridge. Voltage drops IR and j/X c = jlj(2nfC) must add to V A0 \ this addition must be carried out at right angles because of the j coefficient of the reactance term. Then, by geometry, point £ must always lie on the semicircular locus with a constant diameter equal to V AD , as shown in Fig. 17.7(b). As either R or C is varied, the point £ moves "-v E (a) (b) Figure 17.7 (a) Phase shirt control of an SCR; (b) phase shift analysis by circle diagram. 428 Power Control around the circle and voltage V c lags the SCR anode voltage by angle 6, ; the magnitude of V c remains constant at one-half of V AD . The lag angle 8, may be found from the circuit constants and the geome- try of the triangle as tan*i = - InfCR (17.5) (17.6) l/(2;r/C) If R is replaced with an inductor L and C with a resistor, then tan*L_^ If the range of variation of these components is sufficiently great, the angle 0, may be varied nearly from 0° to 180°, resulting in a variation of the average value of SCR current as indicated in Fig. 17.4(a). Diode D is present to prevent gate current on the negative half cycle and resistor R, serves to limit the forward gate current to a safe value. A common application of the UJT is in triggering an SCR, as shown in the typical circuit in Fig. 17.8. Diode D is incorporated to synchronize the gate signal with the positive anode of the SCR. With terminal A and the SCR anode positive, the diode blocks current and transistor Q is off. Capacitor C is then able to charge through control resistor R„ introducing a lime delay in each positive half cycle before the capacitor voltage builds up to V p and triggers the UJT. This buildup of voltage is shown from i to /, in Fig. 17.8(b) and is determined by the time constant CR X . When the UJT triggers, its emitter voltage falls and C is discharged through the UJT and R 2 . The sharp pulse of discharge current produces a peaked gate voltage for the SCR, as shown between /, and i 2 in Fig. 17.8(c), and the SCR turns on. The magnitude of the triggering current for the SCR is controlled by resis- tor R 2 . The circuit provides a triggering delay in each cycle and also provides a pulse waveform for precise triggering of the SCR. The time of triggering or the angle 6, is controllable by resistor R x . On the negative half cycle at A, diode D supplies voltage to Q and this transistor conducts and acts as a short circuit across C. The charging of C then starts precisely at the beginning of each positive half cycle at A. Resistor R x must vary within limits so that the peak point triggering current l„ can be obtained from the I 22 V source. Thus R x must be limited as V - V £>R* (17.7) to turn on the UJT. At the valley point the emitter current must fall below /, to turn off the UJT: that is, (17.8) Triggering the SCR (a) »EB Vp~ '„ ' y (b) LA to Figure 17.8 (a) Phase control with a unijunction trigger; (b) and (c) triggering waveforms. The steady UJT current must not produce a voltage equal to the gate voltage across R z ; this places a limit on R 2 . Example: A typical UJT is rated P t = 300 mW y„ = 35 V tsbmk) = 2 A R BB = 7000 ft i*(m) = 50 mA tj = 0.6 430 Power Control Typical circuit values may be chosen as V BB = 30 V, V r — 1 V, /„ = 10 /iA, and /, = 10 mA. Using Eq. 17.3, y, - 1Vbb + 0.7 = 0.6 x 30 0.7= 18.7 V WithEq. 17.7 V V. 30 - 18.7 11.3 , ., l06a . R With Eq. 17.8, V- y. 30-1 29 _ 290 oq</? ^TT 10 X io-» - To^ - 290 °" < R * Therefore we have available the range of 1. 1 3 MQ to 2900 Q for the varia- tion of R x , in controlling 9, for triggering the SCR. 17.5 The Controlled Polyphase Rectifier Most industrial power is supplied by three-phase circuits. When dc power is needed, it is convenient to employ a polyphase rectifier, one form of which is shown in Fig. 17.9. This is a bridge form of circuit, in which two rectifier elements conduct in series at a given time. Control of the starting lime of current conduction in SCR,, SCR 2 , SCR 3 is furnished by a three-phase adaptation of the unijunction transistor circuit shown in Fig. 17.8. Each diode conducts at the lime its corresponding SCR turns on. More complex circuits are used for providing larger amounts of power. i ii> Figure 17.9 Three-phase controlled bridge rectifier circuit. Shunt-Wound DC Motor Control 431 17.6 Shunt-Wound DC Motor Control The speed-control circuit for a dc shunt-wound motor illustrates the ap- plication of some of the principles previously discussed. A simplified circuit is shown in Fig. 17.10, which operates by controlling the triggering time of an SCR so as to vary the average voltage applied to the motor armature. The UJT circuit is similar to that of Fig. 17.8, with diode D supplying a positive voltage to the UJT only on the half cycle in which the SCR anode is also positive. Current from D charges C through R x and when the capacitor voltage reaches V„ of the UJT, the latter triggers and discharges C through R . This sharp pulse of current produces a pulse of gate voltage for the SCR and it is triggered on. The current of the SCR is the armature current of the motor, occurring in partial half-wave pulses as shown in Fig. 17.10(b). Adjustment of R, controls the triggering angle 9, and thereby the average current to the motor. The result is variation of motor speed. Field AC (a) 0, (b) Figure 17.10 DC motor control circuit; (b) waveform of current. 432 Power Control ^ Review Questions 433 If ihc motor is heavily loaded, it tends to slow down, the voltage across the armature will be reduced, and a larger voltage will appear at diode D and across the control circuit. This larger voltage decreases the time required to charge C and trigger the SCR and yields an earlier 0, and a longer current pulse to the armature. This longer pulse tends to speed up the motor and compensates for motor loading. Speed regulation of about 10 per cent is possible. The motor field current is supplied by a separate bridge rectifier. 77.7 Comments We now have a family of power control switches. Since all units of the family are basically similar to the SCR, we have discussed applications only in terms of that unit. A listing of the devices seems worthwhile, however, and is pre- sented here: SCR: Behaves as a rectifier diode, blocking current in the forward direction until a current pulse of sufficient magnitude is applied to the gate electrode. Thyristor: A general name for the entire family of power control switches but most usually applied to the device we here call the SCR. Triac: A two-way conduction version of the SCR, with current trig- gering by a gate pulse. The action of the gate controls the time of triggering in both current directions. Diac: A two-electrode, three-layer device acting as two inverse-parallel diodes. It conducts in either direction after the applied voltage exceeds a value called the breakover voltage. <$r cr (b) (a) © (c) (d) Fifcure I7.lt (a) Triac; (b) SCR ; (c) diac; (d) GTO. GTO: A gale-turn-off switch; a one-way device with turn-on cha- racteristics as in the SCR. By driving a sufficient negative current into the gate, the GTO can also be turned off. Circuit symbols for these devices are shown in Fig. 17.11. For further information, reference should be made to the manuals of several manu- facturers, as SCR Manual, G.E. Semiconductor Products Dept., Electronics Park, Syracuse, N.Y. RCA Solid-Stale Power Circuits, SP-52, RCA, Somervillc, N.J. 08876. Westinghouse SCR Designer's Handbook, Weslinghouse Corp., Semi- conductor Division, Youngwood, Pa. REVIEW QUESTIONS 17.1 What is an SCR? 17.2 Explain the process of cumulative current buildup when an SCR is gated to turn on. 17.3 What is the typical turn-on time of an SCR? 17.4 What turn-off lime is expected for an SCR? 17.5 Explain the SCR action in the different current regions of Fig. 17.2. 17.6 What is meant by the holding current? 17.7 How do you turn off an SCR? 17.8 What is a UJT? 17.9 What is the intrinsic standoff ratio? 17.10 How is t] (eta) measured? 17.11 Explain the process lhat occurs in a UJT when it triggers. 17.12 What is the peak voltage in a UJT? 17.13 What is the valley voltage? 17.14 If C is fixed and R is variable, what are the limits on R\fO t is to vary between 0° and 180° in a phase shift bridge? 17.15 What is the function of R, in the gate circuit of an SCR? 17.16 What factors determine the lime between voltage application and triggering of the UJT in the circuit of Fig. 17.8? 17.17 What is the purpose of transistor Q in the circuit of Fig. 17.8? 17.18 Why do we not have to use two sets of SCR elements in the polyphase bridge rectifier of Fig. 17.9? 17.19 Explain the method by which speed is controlled in the motor circuit of Fig. 17.10. 434 Power Control PROBLEMS 17.1 The ac supply to an SCR half-wave rectifier is 240 V rms. When the load resis- tance is 1000 fi, what are the dc load currents when the SCR is triggered at 0°, 40°, 90°, and 135°? 17.2 A 10-J2 load is connected to a 120-V rms supply line through an SCR. The average load current is to be varied between 3.0 and 0.5 A. What range of triggering angles is needed ? 17.3 A 10-12 load is supplied with an average current from a 120-0-120 V center- tapped transformer through a full-wave SCR rectifier circuit. The load power is to be varied between 100 and 40 W. (a) What arc the load voltages ? (b) What is the range for the triggering angle ? 17.4 A phase shift bridge at 60-Hz is to control an SCR from full on to 20 per cent of full-on current. If C = 0.7 //F, find the range of variation of R. 17.5 A phase shift bridge at 60-Hz is to control an SCR from 10 per cent to full-on current. The value of C = 0.15 fiF. What is the range needed for /?? 17.6 In Fig. 17.12, R, = 5000 Jl, C, = 0.5 /*F, and R L - 60 fi. What is the angle 0,, and what is the average load current /„ for V ■ 60 V? 17.7 In Fig. 17.12, /?, = 2500 O. and R L - 10 fi. What value of C, will cause the SCR to trigger at 50°? SCR Figure 17.12 17.8 An SCR is used to control the power into a 1000-W, 57-fi, heater element from a 540-V rms circuit. What triggering angles should be used for |, J, and I rated heat ? 17.9 A UJT has R l0 - 5000 Q and /? 2 = 6000 Q. What is the value of rjl With V BB = 25 V, what is the expected peak voltage? Index ^4/3 plot, tabic. 219 Acceptor atom, 10 Active devices, 48 Active network, 50 Adder circuit, 399 Addition, binary, 382 a (alpha), 70 Amplification factor: transistor, 70 triode, 148 Amplifier: band limits, 167 bandpass, 261 bass boost in, 191 buffer. 322 cascodc, 252 differential, 228 common-mode rejection, 232 direct-coupled, 225 FET: basic circuits, 132 common-drain, 137 common-source, 136 design of, 140 Amplifier (com.) FET (com.) low-frequency response, 175 source resistor, 179 gain of a cascade, 59 gain stability of, with feedback, 217 normalized gain of, 168 operational, 238 as comparator, 245 definitions, 249 for differentiation, 244 frequency compensation, 246 for integration, 243 inverting, 238 millivoltmetcr, 245 noninverling, 240 offset voltage and current, 249 RC amplifier, 323 scaling in, 244 single-ended output, 250 slew rate, 247 summing, 242 unity-gain isolator, 242 pentode, 154 phase angle of, 168 power, 283 435 436 Index Index 437 ^ Amplifier (com.) power (com.) Class A, 286 Class AB, 298 Class B, 298 Class B linear. 307 Class C, 284, 333 conversion efficiency of, 288 distortion of, 293 output transformer-less, 302 thermal environment, 290 push-pull, 297 Class B, 300 stagger-tuned, 271 transistor: A, to A v relation, 81 basic forms, 74 bias-stabilized, 107 cascaded, 164 C-E, 82 at high frequency, 188 C-C. 85 C-E, 78 equivalent circuit of, 75 design of, 107 comparison of performance, tabic, complementary symmetry, 306 differential, 228 constant-current bias for, 236 single-ended, 231 emitter follower, 85 design, 1 14 fixed bias, 100 design, 105 four-resistor bias, 102 design, 107 frequency response, 164 high-frequency response, 182 integrated, 225 low-frequency response, 168 pass band, 165 performance, table, 87 phase inverter, 304 single-tuned, 268 stability ratio, 105; table, 115 treble boost in, 192 voltage-feedback bias for, 1 10 voltage reference for, 237 triode: basic circuits, 148 cathode follower, 155 Amplifier (conl.) triode (conl.) cathode resistor, 179 common-cathode, 153 grounded-grid, 157 low-frequency response, 175 video, 261 scrics-pcakcd, 277 shunt-peaked, 273 time delay, 275 Anode, 21 vacuum tube, 145 Armstrong, E.H., 367 Armstrong oscillator, 318 ASCII code, 379 Astable multivibrator, 400 Atoms, 2 acceptor, 10 Bohr theory, 2 donor, 9 Automatic frequency control, 348 Automatic volume control, 336 B Balanced modulator, 338 Bandwidth: AM signal, 330 cascaded amplifier, 189 definition, 249 FM signal, 342 inprovement by feedback, 204 information, 355 resonant circuit, 265 Bardeen and Brattain, 64 Base, 65 Bass boost, 191 BCD code, 378 Beat frequency, 358 Bel, 58 Bell, Alexander Graham, 58 Bias: constant-current, 256 FET, 127 fixed, 100 four-resistor circuit, 129 stability, 105 stabilized, design for, 107 transistor, 96 voltage feedback, 1 10 circuit, 112 Bias currents, 73 Binary addition, 382 Binary arithmetic, 377 Binary code, 374, 378 Binary-coded-decimal, 378 Binary number, 374 Binary point, 376 Binary signals, decoding of, 413 Bistable multivibrator, 400 Bit, 354 definition, 376 parallel and serial processing of, 381 Black box, 48 feedback concepts, 199 Bohr atom theory, 2 Breakover voltage, diac. 432 Bridge rectifier circuit, 25 BufTer amplifier, 322 BVooo, 122 Byte, 379 Capacitor: blocking, 166.317 bypass, 151, 177 filter, 27 speed-up, 392 in flip-flop, 402 voltage-variable, 17 Capture effect, 367 Carrier frequency. 327 Carry bit, 400 Cascaded amplifier, 189 Cascodc amplifier, 252 Cathode, 21 vacuum tube, 145 Cathode follower, 148. 155 Cathode-ray oscilloscope, 370 Cathode-ray tube, 159 Center frequency, 342 Channel, 120 Clamper, 41 Class A operation, 284 Class AB operation, 298 Class B amplifier: linear, 307 operation, 284 Class C amplifier: modulated, 333 operation, 284 Clipper, 38 double diode, 41 Clock, 381 trigger, in RS flip-flop, 403 CMOS: JK flip-flop, 406 logic circuits, 395 manufacture, 398 CMRR, 233, 250 Code, cxcess-3, 421 Coefficient of coupling, 269 Cold-cathode emission, 147 Collector, 65 Collector resistance, 68 Colpitis oscillator, 315 Common-cathode amplifier: circuit, 148 pentode, 154 triode, 153 Common-drain amplifier, 137 design, 140 Common mode, definition, 232 Common-mode input, 228 Common-mode rejection ratio, 233, 250 Common-mode voltage gain, 249 Common-source amplifier, 1 36 Comparator, 245 Complement, 377 Complementary symmetry circuit, 306 Conductance, 77 Conduction, 5 Constant-current bias, 236 Control generator, 56 Conversion gain, 340 Covalcnt bond, 5, 8 CRf, 29 Critical coupling, 269 Crossover distortion, 306 Crystals. 3. 10 piezoelectric, 319 Current: definition, 1,7 diode, 13, 14 forward, 12 h- bo, 67 in injunction, 13 reverse saturation, 1 3 transistor, 67 transistor, table, 99 Current amplification factor, 70 relation with A„ 81 Index 439 438 Index Equivalent circuit (com.) Filter (com.) Current division factor, 170 Diode-transistor logic (DTL), 390 Thevenin, 51 capacitor (com.) Current feedback, 207 Direct-coupled amplifier, 225 transistor: surge resistor for, 31 Current generator, controlled, 56 Directly-heated filament, 147 g m model, 78 C/?/ factor in. 29 Current-source equivalent circuit, 52 Discriminator, frequency, 344 correction voltage from, 368 high-frequency, 181 /j-parameter, 75 n (pi), 31 n-R, 34 D Dissipation locus, 97 hybrid-K, 180 SSB signal. 362 Darlington compound transistor, 250 Dc level shifter, 237 Decade, frequency, 168 Decibel, 58 Decimal counting, 414 Decimal numbers, 375 Decimal point, 375 Decoding matrix, 413 Deletion region, 13 in FET, 121 Detection, 326 AM: linear, 334 product, 340 FM: discriminator, 344 ratio detector for, 347 radar, 370 Deviation ratio, 342 Diac, 432 Differential amplifier, 228 as comparator, 245 Differential-mode voltage gain, 250 Differentiation, 244 Diffusion, 11, 89 Digital circuits, 374 Diode: breakdown of, 15 capacitance of, 1 7 clamper, 41 clipper, 38 double, 41 current in, 14, 23 equation, 13 ideal, 21 junction, 1,11 light-emitting, 16 photo, 16 rectifier, 13, 21 steering, 403 symbol for, 14 Zener, 15 Diode modulator, 331 balanced, 339 Distortion: allowable, 296 crossover, 306 frequency, 165 nonlinear, 206, 293 reduction by feedback, 206 Divide-by- 10 counter, 416 Donor atom, 9 Dopplcr effect, 370 Drain, 120 DSB, 330 Edison effect, I EHF, 371 Electron, 1,2 Electron gun, 159 Electron-hole pair, 7 Electron volt, 8 Element, 2 Emission of electrons, 146 Emitter, 65 Emitter-coupled logic (ECL), 394 Emitter follower, 85 circuit design, 1 14 feedback amplifier, 215 phase inverter, 306 Emitter resistor, 177 Energy: forbidden, 7 gap, 7 Enhancement mode, 1 25 Epitaxial growth, 91 Equivalent circuit: C-B amplifier, 83 C-C amplifier, 85 C-E amplifier, 75 current source, 52 definition, 49 FET, 135 high-frequency, 181 //-parameter, 56 Norton, 52 SCR, 422 triode, 152, 182 UJT, 426 voltage-source, 51 Exccss-3 code, 421 Fan-in, 388 Fan-out, 388 Feedback: advantages, 221 bandwidth improvement. 204 black-box analysis, 199 closed-loop gain, 201 control of resistances. 207 table, 209 current, 207 current-series, 209 in decimal counter, 415 emitter follower, 215 gain margin in, 220 gain stability with, 217 internal gain with, 200 measure of, 201 multiple-stage, 216 oscillator, 201 phase margin in, 220 positive, 201 limitation in receiver, 359 principles of, for oscillators, 313 reduction of distortion. 206 stabilization of gain, 202 voltage, 207 voltage-series, FET, 213 voltage-shunt, 212 Feedback factor, 201 FET, 120 Figure of merit : Q, 263 transistor, 186 in C-B circuit, 189 Filament, 147 Filter: capacitor, 27 First breakdown, 290 Flip-flop. 400 decimal counting, 414 shift register, 412 Fluorescent screen, 161 FM system, 367 pre-emphasis circuits in, 193 Forbidden energy, 7 Foster-Seeley discriminator, 345 Frequency classification, table, 371 Frequency compensation, 246 Frequency deviation, 341 Frequency distortion, 165 Frequency emphasis, 191 insertion loss with, table. 192 Frequency modulation, 341 Frequency multiplex, 362 Frequency translation, 360 Full-wave rectifier circuit, 24 Gain-bandwidth product, 187 Gain, voltage, 77 Gain margin, 220 Gap energy, 8 Gate: FET, 120 logic, 383 and. 383 diode, 386 fan-in of, 388 fan-out of. 388 nand, 385 nor, 385 not, 384 or, 384 Gate-turn-off switch, 433 Germanium, 2, 5, 8 Glitch, 394 Km- FET, 133 transistor, 77 triode, 150 440 Index Index 441 Grid, 145, 151 Grounded-grid amplifier, 157 H Half-power frequency, 167 Half-wave rectifier circuit, 22 Hartley oscillator, 315,316 Hartley-Shannon law, 357 Heat sink, 291 Heterodyne interference, 358 Hexadecimal system, 381 HF, 371 Holding current, 424 Hole, 6 h parameters: conversion, 81 current gain, 70 definitions, 55 equivalent circuit, 56 Hybrid parameters, 56 Hybrid-n equivalent circuit, 180 Hydrogen atom, 2 I Icbo, 67 as temperature function, 99 Ideal transformer, 285 Image frequency, 360 Impurities, semiconductor, 8 Indirectly-healed cathode, 197 Information, 354,355 Hartley-Shannon law for, 357 Injection of charges, 12 Input offset current, 250 Input offset voltage, 250 Insertion loss, table, 192 Insulator, 4 Integrated circuit: CMOS, 395 logic, 389 manufacture of, 253 passive elements in, 255 sheet resistance of, 255 silicon, 253 Integration, 243 Intermediate frequency, 262, 358 Intrinsic conduction, 7 Intrinsic standoff ratio, 425 Inverter, 383 CMOS, 395 Ion, 3 Ionizing energy, 3 JFET, 120 JK flip-flop. 405 Junction, 1 1 voltage-current equation for, 13 Lattice, 3 LED, 16 LF, 371 Limitcr, 344 emitter-coupled, 346 Load line: ac, 288 dc. 72 forFET. 125 Logic circuits, 383 adder, 399 CMOS, 395 inverter, 395 manufacture, 398 nand, nor, 396 diode (DL). 386 diode-transistor (DTL), 390 emitter-coupled (ECL), 394 integrated, 389 resistance-transistor (RTL), 392 transistor-transistor (TTL), 393 voltage levels in, 386 M Majority carriers, 10 Masking, 90 Matched load, 54 Materials, properties of, table, 4 Matrices, decoding, 413 Maximum power output, 53 Metal, 4 Metric magnitudes, 4 MF, 371 Miller effect, 180 Millivoltmctcr circuit, 245 Minority carriers, 10 Modulated amplifier, 333 Modulation, 326 amplitude (AM). 327 bandwidth for, 330 beat frequency. 358 carrier frequency, 327 frequency spectrum, 327 heterodyne interference in, 367 "monkey chatter" in, 367 power spectrum of, 330 side frequencies, 328 single sideband, 337 comparison of AM and FM, 349, 366 frequency (FM), 327 bandwidth, 342 capture effect, 367 center frequency, 342 deviation ratio, 342 frequency deviation in, 341 frequency spectrum, 341 generation, 344 interference in, 366 narrow band, 344 wide band, 344 phase (PM), 327 pulse, 327 Modulation factor, 328 Modulator: balanced, 338 Class B, 334 diode. 331 Monkey chatter, 367 Monostablc multivibrator, 400 MOSFET, 123 Motor control, 431 Multiplex, frequency, 362 Multivibrator, 374,400 astablc, 408 bistable, 401 flip-flop, 401 CMOS, 406 JK, 405 RS circuit, 402 scalc-of-four, 404 sale-of-two, 403 toggling (T), 403 free-running, 408 synchronization of, 410 monostablc, 407 Schmitt trigger, 411 N nand circuit, 391,396 Negative feedback, 199 (see Feedback) Negative logic, 386 Network : active, 50 current-source equivalent, 52 equivalent, definition, 49 maximum power transfer, 53 Norton, 52 one-port, 49 ^-matching, 308 Thevenin, 51 two-port, 49 /; parameters for, 54 voltage-source equivalent, 51 Neutron, 2 Noise, 353 in logic circuits, 394 Noise figure, 354 nor circuit, 396 Normalized gain, 168 Norton circuit, 52 not operation, 383, 388 Number systems, table, 380 Nyquist criterion, 219 Octal system, 379 Offset current, 249 Offset voltage, 249 One-shot multivibrator. 407 Operational amplifier, 225, 238 comparator, 245 definitions, 249 differentiation with, 244 frequency compensation, 246 integration with, 243 inverting, 238 millivoltmeter, 245 noninverting, 240 offsets, 249 slew rate, 247 summing, 242 unity-gain isolator, 242 Oscillator: Armstrong, 318 astablc multivibrator form of, 408 Colpitts, 315 442 Index Index 443 Oscillator (com.) drain-tuned FET, 322 Hartley, 315,316 piezoelectric control of, 319 principles of, 313 resistance-capacitance feedback, 322 Output circuit, without transformer, 302 Overshoot, 271 Pair generation, 7 PAM, pulse-amplitude modulation, 327 Parallel processing of data, 381 Parallel-resonant circuit, 263 bandwidth, 265 as a tank circuit, 317 Parameters: //. 54 conversion of, 74 small-signal, 74 Passive elements, 255 PCM, pulse-code modulation, 327 PDM, pulse-duration modulation, 327 Peak reverse voltage, 23 Pentode, 145. 150 Phase inverter, 304 complementary symmetry form, 306 emitter-coupled, 231 Phase margin, 221 Photodiode, 16 Photoelectric emission, 147 Photoisolator, 16 Photon, 1 Photoresist lacquer, 90 n (pi) filter, 31 n-matching network, 308 n-R filter, 34 Piezoelectric crystals, 319 Pinch-off, 121 PMMC instrument, 37 Polyphase rectifier, 430 Port, 48 Position, in number system, 375 Positive logic, 386 Power : control of. 422 decibel, 58 maximum, 53 Power gain, definition, 79 Power ratio, in dB, 59 Prc-cmphasis circuit, 193 Product detector, 340 Proton, 2 PRV, 23 Pulse, 271 Pulse stretcher, 407 Punch-through, 290 Push-pull circuit, 284. 297 phase inverter for, 304 Q, circuit, 263 Q point, sec Quiescent point Quartz crystal, 319 Quiescent point, 73 choice of, 96 Class fl, 300 variation of, 99 R Radar, 368 Radio-frequency amplifier, 261 Radio-frequency choke, 3 1 7 Radio signal, classification of frequencies, 371 Radio systems, 353 Radix, 374 Ratio detector, 347 RC amplifier, 164 Real time, 327 Receiver: FM, 368 radar, 370 SSB, 363 superheterodyne, 358 Rectifier, 21 diode, 13 silicon-control (SCR), 422 triggering of, 427 Rectifier circuit: bridge, 25 full-wave, 24 half-wave, 22 polyphase, 430 SCR, 424 voltage-doubling, 35 Rectifying ac voltmeter, 37 Repetition rate, 272 in radar, 370 Reset-set (RS) flip-flop, 402 Resistance-transistor logic (RTL), 392 Resistivity, 4 Resonance, 263 Reverse saturation current, 13 transistor, 67 Ripple factor, 27 Rise time, 271 Rochclle salt, 320 RS flip-flop, 402 Saturation line, 68 Scale factor, 244 Scalc-of-four circuit, 404 Scale-of-two circuit, 403 Schmitt trigger, 41 1 Secondary emission, 147 Second breakdown, 290 Selectivity, 261 Semiconductor: atomic arrangement in, 2 defined, 5 impurity, 8 majority carriers, 10 minority carriers, 10 resistivity of, table, 4 Series processing of data, 381 Series resonance, 320 Shape factor, 262 Sheet resistance, 255 Shell, energy, 2 Shift register, 412 Shockley, 120 Short circuit limit frequency, 1 86 Sidebands, 329 Side frequencies, 328 Signal-to-noise ratio, 354 Silicon, 5 atomic arrangement, 2 forbidden energy, 8 integrated circuit, 227 Silicon-control rectifier (SCR), 422 in motor control, 431 polyphase circuit, 430 triggering of, 427 Single sideband system, 337 advantages, 366 receiver, 360 transmitter, 362 Skirt selectivity, 360 Slew rate. 247 definition, 250 Small signal, defined, 98 Source, 50 FET, 120 Source follower, 132,137 Speedup capacitance, 392 Square wave, harmonics in, table, 273 SSB, 337 Stabilizing ratio, 105 for C-E amplifier, 110 comparison, table, 115 Stagger-tuned amplifier, 271 Static, 353 Steering diodes. 403 Summing operation. 242 Superheterodyne receiver, 358 Tor FM, 368 for radar, 371 Surge resistor, 31 Sweep voltage, 1 59 Switch, 18,21 Switching time, flip-flop, 402 Synchronization, of multivibrator, 410 Tank circuit, 317 Tape recording, 193 Temperature, absolute zero, 6 T flip-flop, 403 Thermal derating curve, 292 Thermal noise, 353 Thermal resistance, 291 Thermionic emission, 146 Thevenin equivalent circuit, 51 Thyristor, 432 Time delay, 275 Total harmonic distortion, 296 Totem pole, 393 Transceiver, 363 Transconductancc : conversion, 340 FET, 133 transistor, 77 C-B connection, 83 triodc, 150 Transfer curves, 228 FET, 133 Index Transformer: double-tuned, 269 ideal, 285 Transistor, 64 alloyed junction, 89 bipolar, 64, 120 CMOS, 395 complementary, 306 current relations, table, 99 Darlington compound, 250 defined currents and voltages, 64 derating curve for, 292 epitaxial growth, 91 field effect (FET), 64,120 bias, 127 characteristics, 132 dcload line, 125 depletion mode, 121 enhancement mode, 125 equivalent circuit for, 135 high-frequency model, 181 junction, 120 MOS, 123 pinch-off region in, 121 symbols, 125 iransconductance, 133 transfer curve, 133 variable resistance, 142 figure of merit, 186 frequency limits, 185 gain-bandwidth product, 187 grown junction, 89 high-frequency model, 181 hybrid-* model, 180 junction, 65 manufacturing techniques, 89 mesa, 89 operating region, 96 planar, 89 reverse saturation current, 67 saturation line, 68 thermal environment, 290 transconductance, 77 unijunction (UJT), 425 for motor control, 431 unipolar, 64, 120 volt-ampere curves, 68 voltage limitations, 290 Transistor amplifier: basic types, 74 bias circuit design, 130 Transistor amplifier (com.) fixed bias for, 100 four resistor circuit, 102 FET, 129 in not operation, 388, 390 voltage feedback with, 123 Transistor-transistor logic (TTL), 393 Translation, frequency, 326, 329, 339 Transmitter: AM, 357 FM, 367 radar, 370 SSB, 362 Treble-boost circuit, 192 Triac, 432 Trigger circuit: for SCR, 427 Schmitt, 411 trailing edge, 405 Triodc, 145 amplification factor, 148 characteristics, 148 equivalent circuit, 152 gain-bandwidth product, 187 high-frequency model, 182 notation, 145 planar, 146 symbol, 147 transconductance, 150 Turnover frequencies, 191 in FM, 193 Turns ratio, 285 U UHF, 371 Undcrcoupling, 269 Unijunction transistor (UJT), 425 in motor control, 431 for triggering, 428 Unity gain isolator, 242 Vacuum tube, 145 Valence electron, 2 VHF. 371 Video amplifier, 261 Voltage, UJT: peak, 426 valley, 426 Index 445 Voltage-doubling rectifier circuit, 35 Voltage feedback, 207 bias, 110,112 Voltage generator, controlled, 56 Voltage multiplier, 37 Voltage reference, 237 Voltage regulator, Zencr, 15 Voltage-source equivalent, 51 Voltage-variable capacitor (VVC), 17 Voltage-variable resistance (VVR), 142 Voltmeter: peak, 38 rectifying, 37 Zencr diode, 1 5 Zero level, 59